Abstract: A gasket and mandrel assembly, including a gasket having an annular main body portion with an anchor flange and a pipe sealing portion. The gasket is foldable between a folded position in which the pipe sealing portion is disposed substantially within the main body portion and an unfolded position in which the pipe sealing portion extends outwardly of the main body portion along its longitudinal axis. A pair of mandrels are respectively fitted on opposite sides of the folded gasket to enclose most of the gasket for casting the gasket within a wall in a concrete structure. At least one of the mandrels includes an annular outer surface aligned parallel or substantially parallel with the longitudinal axis of the gasket.

Abstract: A gasket and mandrel assembly, including a gasket having an annular main body portion with an anchor flange and a pipe sealing portion. The gasket is foldable between a folded position in which the pipe sealing portion is disposed substantially within the main body portion and an unfolded position in which the pipe sealing portion extends outwardly of the main body portion along its longitudinal axis. A pair of mandrels are respectively fitted on opposite sides of the folded gasket to enclose most of the gasket for casting the gasket within a wall in a concrete structure. At least one of the mandrels includes an annular outer surface aligned parallel or substantially parallel with the longitudinal axis of the gasket.

Abstract: A remapping method and apparatus is employed by a memory controller system which includes a microprocessing section which couples to a memory section. The memory section includes a partially good bulk random access memory constructed from a plurality of bit wide chips containing a predefined small number of row or column faults randomly distributed. System columns of chips are organized into a plurality of groups or slices, each of which provide a different predetermined portion of the locations within the partially good bulk memory. A defective-free memory having substantially less capacity is similarly organized. Both memories couple to a static memory which is remapped under the control of the microprocessing section. Prior to remapping, the microprocessing section generates a "slice bit map" indicating the results of testing successive bit groups/slices within the bulk memory locations.

Abstract: A memory controller includes a partial defective bulk random access memory having a number of word locations constructed from a plurality of bit wide chips containing a predefined small number of random row or column faults. System columns of chips are organized into a plurality of groups, each group providing a different predetermined portion of the number of word locations. A defect-free memory system having substantially less capacity is similarly organized. Both memories couple to a static memory which stores column addresses associated with good memory locations and slice bit codes specifying the operational status of corresponding bit groups of word locations within both memories. During operation, read/write control circuits read and write valid words from group of bit locations from locations of both memories specified by slice bit codes.