Abstract: Flow logic supports concurrency of multiple threads and/or tag IDs to be concurrently communicated across the interconnect while allowing the one or more target IP cores to be able to reorder incoming request transactions from the initiator IP core in a manner that is optimal for that target IP core while relieving that target IP core from having to maintain the sequential issue order of transaction responses to the incoming request transactions in the thread or tags when processed by the target IP core. The flow logic cooperates with the reorder storage buffers to control an operation of the reorder storage buffers as well as control issuance of at least the request transactions from the initiator IP core onto the interconnect in order to maintain proper sequential ordering of the transaction responses for the thread or tags when the transaction responses are returned back to the initiator IP core.

Abstract: Flow logic supports concurrency of multiple threads and/or tag IDs to be concurrently communicated across the interconnect while allowing the one or more target IP cores to be able to reorder incoming request transactions from the initiator IP core in a manner that is optimal for that target IP core while relieving that target IP core from having to maintain the sequential issue order of transaction responses to the incoming request transactions in the thread or tags when processed by the target IP core. The flow logic cooperates with the reorder storage buffers to control an operation of the reorder storage buffers as well as control issuance of at least the request transactions from the initiator IP core onto the interconnect in order to maintain proper sequential ordering of the transaction responses for the thread or tags when the transaction responses are returned back to the initiator IP core.

Abstract: Flow logic supports concurrency of multiple threads and/or tag IDs to be concurrently communicated across the interconnect while allowing the one or more target IP cores to be able to reorder incoming request transactions from the initiator IP core in a manner that is optimal for that target IP core while relieving that target IP core from having to maintain the sequential issue order of transaction responses to the incoming request transactions in the thread or tags when processed by the target IP core. The flow logic cooperates with the reorder storage buffers to control an operation of the reorder storage buffers as well as control issuance of at least the request transactions from the initiator IP core onto the interconnect in order to maintain proper sequential ordering of the transaction responses for the thread or tags when the transaction responses are returned back to the initiator IP core.

Abstract: A method and apparatus for transmitting data over a clock-gated mesochronous clock domain boundary in an interconnect network of an integrated circuit. New data is received into storage buffers within a sender domain. The data is synchronized by sending time-controlled signals from storage elements in a sender control within the sender domain to corresponding inputs in a receiver control signal path in a receiver domain. Multiplexers are signaled to sequentially transmit the data from the storage buffers across the domain boundary to the receiver domain according to the time-controlled signals received from the sender control by the receiver control signal path, where the multiplexers receive signals from a data path pointer counter in communication with the receiver control signal path.

Abstract: A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module is used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.

Abstract: A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.

Abstract: A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

Abstract: A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

Abstract: A communication protocol provides high-speed transfers of parallel data between an origination end and a destination end. The protocol involves regularly transmitting data from the origination end to the destination end, including transmitting idle data from the origination end when the destination end is busy and during periods when no commands, data or statuses are pending. When the destination end is not busy, data is sent from the origination end to the destination end by: sequentially transferring read or write commands and, according to a write protocol, pending write data; and transmitting idle packets during periods when no commands are pending.

Abstract: In one example embodiment, a high-speed parallel-data communication approach transfers digital data in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines and a clock path. The parallel bus lines are arranged in a plurality of groups, each of the groups including a plurality of data-carrying lines and a clock path adapted to carry a clock signal for synchronizing digital data carried from the first module to the second module. The sets of data are concurrently transferred using the groups of lines of the parallel bus, and at the second module and for each group, the transferred digital data is synchronously collected via the clock signal for the group. At the second module, the data collected for each group is aligned.

Abstract: A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, the rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized subset of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.

Abstract: An access control device inhibits data transfers on a bus between unauthorized initiator-target pairs. A permission-matrix is maintained that identifies the access permission of each initiator relative to each target. The access device monitors the bus and determines the identification of the initiator and the intended target. If the initiator has the appropriate access rights to the target, the bus communication is permitted to occur, otherwise the communication is blocked, and an error signal is asserted. To provide further security, the identifier of initiators that are local to the access control device are communicated to the access control device via a direct wired connection to each initiator.

Abstract: A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, the rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized subset of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.

Abstract: In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

Abstract: A system architecture and method allows for both synchronous and asynchronous communications on a common bus. Components that are able to reliably communicate via the bus using a synchronous interface are configured to communicate synchronously. Components that would require an unacceptable reduction in system-clock frequency to achieve synchronous communications are configured to communicate asynchronously. A bus controller facilitates bus arbitration, as well as synchronous-to-synchronous, synchronous-to-asynchronous and asynchronous-to-synchronous, and asynchronous-to-asynchronous transfers between components. To accommodate for physical layout dependencies, the components include a bus interface that is configurable for either synchronous or asynchronous communications, so that the determination of whether communications will be synchronous or asynchronous can be made after the layout is completed.

Abstract: A communication protocol provides high-speed transfers of parallel data between an origination end and a destination end. The protocol involves regularly transmitting data from the origination end to the destination end, including transmitting idle data from the origination end when the destination end is busy and during periods when no commands, data or statuses are pending. When the destination end is not busy, data is sent from the origination end to the destination end by: sequentially transferring read or write commands and, according to a write protocol, pending write data; and transmitting idle packets during periods when no commands are pending.

Abstract: In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

Abstract: A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

Abstract: A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

Abstract: The timing characteristics of an integrated circuit design with an original combination-logic module can be potentially improved by moving an input signal with problematic timing in the original module so that it controls an output multiplexer in a revised module. The revised module includes two submodules. The first submodule provides the desired logic result where the late signal is low; the second submodule provides the desired logic result where the late signal is high. The multiplexer is controlled by the late signal so that its output is the desired logic result under steady-state conditions. If there are other input signals requiring timing advancement, the method can be reiterated. The method can be iterated until specifications are met or it is clear that the method cannot meet specifications by additional iterations.