Abstract: A supply reference voltage circuit is coupled to an output node, a supply voltage node and a supply reference voltage node and is operable to connect the output node to the supply reference voltage node and prevent current flow through an output device coupled to the output node in response to sensing a low voltage level at the supply voltage node and a non-zero voltage at the output node. The circuit is further operable to connect the supply reference voltage node to the supply voltage node in response to the voltage at the output node being a threshold voltage above the voltage at the supply voltage node. The circuit is further operable to bypass a blocking diode in response to sensing a high voltage level at the supply voltage node.

Abstract: A supply reference voltage circuit is coupled to an output node, a supply voltage node and a supply reference voltage node and is operable to connect the output node to the supply reference voltage node and prevent current flow through an output device coupled to the output node in response to sensing a low voltage level at the supply voltage node and a non-zero voltage at the output node. The circuit is further operable to connect the supply reference voltage node to the supply voltage node in response to the voltage at the output node being a threshold voltage above the voltage at the supply voltage node. The circuit is further operable to bypass a blocking diode in response to sensing a high voltage level at the supply voltage node.

Abstract: A supply reference voltage circuit is coupled to an output node, a supply voltage node and a supply reference voltage node and is operable to connect the output node to the supply reference voltage node and prevent current flow through an output device coupled to the output node in response to sensing a low voltage level at the supply voltage node and a non-zero voltage at the output node. The circuit is further operable to connect the supply reference voltage node to the supply voltage node in response to the voltage at the output node being a threshold voltage above the voltage at the supply voltage node. The circuit is further operable to bypass a blocking diode in response to sensing a high voltage level at the supply voltage node.

Abstract: A voltage reference overshoot protection circuit senses unwanted ringing voltage levels in a driven device such as a backplane and controls the gate voltage to a voltage level control transistor such that a ringing output signal produced by an associated output driver is reduced in response to a control signal dependent on the ringing voltage level.

Abstract: The output control circuit includes: a first high side transistor 56 coupled to an output node 68; a second high side transistor 59 coupled in parallel with the first high side transistor 56; a first transmission gate 72 coupled between a control node of the first high side transistor 56 and a control node of the second high side transistor 59, the first transmission gate 72 is controlled by feedback from the output node 68; a first low side transistor 50 coupled to the output node 68; a second low side transistor 53 coupled in parallel with the first low side transistor 50; a second transmission gate 74 coupled between a control node of the first low side transistor 50 and a control node of the second low side transistor 53, the second transmission gate 74 is controlled by feedback from the output node 68.

Abstract: The invention discloses a method and system for synchronizing external data to an internal timing signal. External data is received in conjunction with a clock input. The clock input has first set of values and a second set of values. The clock input is compared to an internal timing signal having a frequency that is a multiple of the clock input. The internal timing signal is shifted by adjusting the count of a counter if the clock input transitions from the first set of values to the second set of values within a predetermined range of the internal timing signal.

Abstract: There is disclosed a circuit and method for providing bias voltage levels which are precisely controlled as a function of temperature. The circuit is arranged to mix a precise bandgap regulated voltage with a temperature compensated circuit to provide the required output. The temperature compensated circuit is in turn arranged to mimic the temperatue sensitive components in the output circuit.

Abstract: A translator circuit 82 and operation thereof is disclosed including a control signal generator 48 and an ECL output buffer circuit 84. Control signal generator 48 includes a CMOS inverter comprising transistors 52 and 54. The CMOS inverter is connected to a bipolar junction transistor (BJT) 70 which is further connected to as BJT 76. BJT 70 provides a voltage control signal, V.sub.CS, to ECL output buffer circuit 84. BJT 76 is connected as a transistor in a differential pair comprising transistors 76 and 86. An ECL output signal, V.sub.OUT, is generated in accordance with the operational state of transistors 76 and 86 and additional circuitry associated therewith.

Abstract: There is disclosed a circuit and method for providing bias voltage levels which are precisely controlled as a function of temperature. The circuit is arranged to mix a precise bandgap regulated voltage with a temperature compensated circuit to provide the required output. The temperature compensated circuit is in turn arranged to mimic the temperature sensitive components in the output circuit. A reduced voltage level is created which introduces no temperature related voltage changes.

Abstract: An apparatus and method for translating voltages between logic levels is provided having an input section (11), a level shifter section (89) and an output section (137). Input section (11) provides two control voltages to the level shifter section (89) in response to an input signal provided at input terminal (12). Level shifter section (89) comprises two inverters coupled to the control voltages. One inverter comprises p channel field-effect transistor (90) and n channel field-effect transistor (98). Another inverter comprises p channel field-effect transistor (106) and n channel field-effect transistor (114). For each inverter, the channel of the p channel field-effect transistor is over twice as wide as the channel of the n channel field-effect transistors. Each transistor (90, 98, 106 and 114) conducts current in response to a control voltage being anywhere within the voltage range, such that outputs of the inverters transition quickly in reponse to a transition of the control voltages.

Abstract: There is disclosed a circuit and method for converting on/off logic signals from one medium to on/off signals useful in a different medium. The circuit is particularly adapted to translate from positive voltage levels to negative voltage levels. The circuit includes voltage control levels for precisely controlling voltage as a function of temperature, all while only using positive voltage levels on the conversion circuit.