Patents by Inventor Timothy Antesberger
Timothy Antesberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9351408Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.Type: GrantFiled: April 22, 2010Date of Patent: May 24, 2016Inventors: Voya Markovich, Timothy Antesberger, Frank D. Egitto, William Wilson, Rabindra N. Das
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Patent number: 8541687Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin.Type: GrantFiled: April 22, 2010Date of Patent: September 24, 2013Assignee: Endicott Interconnect Technologies, Inc.Inventors: Voya Markovich, Timothy Antesberger, Frank D. Egitto, William Wilson, Rabindra N. Das
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Patent number: 8536459Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.Type: GrantFiled: April 22, 2010Date of Patent: September 17, 2013Assignee: Endicott Interconnect Technologies, Inc.Inventors: Voya Markovich, Timothy Antesberger, Frank D. Egitto, William Wilson, Rabindra N. Das
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Patent number: 8405229Abstract: An electronic package for interconnecting a high density pattern of conductors of an electronic device (e.g., semiconductor chip) of the package and a less dense pattern of conductors on a circuitized substrate (e.g., PCB), the package including in one embodiment but a single thin dielectric layer (e.g., Kapton) with a high density pattern of openings therein and a circuit pattern on an opposing surface which includes both a high density pattern of conductors and a less dense pattern of conductors. Conductive members are positioned in the openings to electrically interconnect conductors of the electronic device to conductors of the circuitized substrate when the package is positioned thereon. In another embodiment, the interposer includes a second dielectric layer bonded to the first, with conductive members extending through the second layer to connect to the less dense pattern of circuitized substrate conductors.Type: GrantFiled: November 30, 2009Date of Patent: March 26, 2013Assignee: Endicott Interconnect Technologies, Inc.Inventors: Timothy Antesberger, Frank D. Egitto, Voya R. Markovich, William E. Wilson
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Publication number: 20130025839Abstract: An organic substrate capable of providing effective heat transfer through its entire thickness by the use of parallel, linear common thermally conductive openings that extend through the substrate, the substrate having thin dielectric layers bonded together to form an integral substrate structure. The structure is adapted for assisting in providing cooling of high temperature electrical components on one side by effectively transferring heat from the components to a cooling structure positioned on an opposing side. Methods of making the substrate are also provided, as is an electrical assembly including the substrate, component and cooling structure.Type: ApplicationFiled: July 25, 2011Publication date: January 31, 2013Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.Inventors: Frank Egitto, Voya R. Markovich, Varaprasad V. Calmidi, Timothy Antesberger, William E. Wilson
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Patent number: 8245392Abstract: A method of making an electronic package designed for interconnecting high density patterns of conductors of an electronic device (e.g., semiconductor chip) and less dense patterns of conductors of hosting circuitized substrates (e.g., chip carriers, PCBs). In one embodiment, the method includes bonding a chip to a single dielectric layer, forming a high density pattern of conductors on one surface of the layer, forming openings in the layer and then depositing metallurgy to form a desired circuit pattern which is then adapted for engaging and being electrically coupled to a corresponding pattern on yet another hosting substrate. According to another embodiment of the invention, an electronic package using a dual layered interposer is provided. Also provided are methods of making circuitized substrate assemblies using the electronic packages made using the invention's teachings.Type: GrantFiled: December 1, 2009Date of Patent: August 21, 2012Assignee: Endicott Interconnect Technologies, Inc.Inventors: Timothy Antesberger, Frank D. Egitto, Voya R. Markovich, William E. Wilson
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Publication number: 20120160547Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin.Type: ApplicationFiled: April 22, 2010Publication date: June 28, 2012Applicant: Endicott Interconnect Technologies, Inc.Inventors: Timothy Antesberger, Rabindra N. Das, Frank D. Egitto, Voya R. Markovich, William E. Wilson
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Publication number: 20120160544Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.Type: ApplicationFiled: April 22, 2010Publication date: June 28, 2012Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.Inventors: Timothy Antesberger, Rabindra N. Das, Frank D. Egitto, Voya R. Markovich, William E. Wilson
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Patent number: 8198551Abstract: A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.Type: GrantFiled: May 18, 2010Date of Patent: June 12, 2012Assignee: Endicott Interconnect Technologies, Inc.Inventors: Robert M. Japp, Kostas Papathomas, John Steven Kresge, Timothy Antesberger
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Publication number: 20120031649Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.Type: ApplicationFiled: April 22, 2010Publication date: February 9, 2012Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.Inventors: Timothy Antesberger, Rabindra N. Das, Frank D. Egitto, Voya R. Markovich, William E. Wilson
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Publication number: 20110284273Abstract: A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.Type: ApplicationFiled: May 18, 2010Publication date: November 24, 2011Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.Inventors: Robert M. Japp, Kostas Papathomas, John S. Kresge, Timothy Antesberger
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Publication number: 20110127664Abstract: An electronic package for interconnecting a high density pattern of conductors of an electronic device (e.g., semiconductor chip) of the package and a less dense pattern of conductors on a circuitized substrate (e.g., PCB), the package including in one embodiment but a single thin dielectric layer (e.g., Kapton) with a high density pattern of openings therein and a circuit pattern on an opposing surface which includes both a high density pattern of conductors and a less dense pattern of conductors. Conductive members are positioned in the openings to electrically interconnect conductors of the electronic device to conductors of the circuitized substrate when the package is positioned thereon. In another embodiment, the interposer includes a second dielectric layer bonded to the first, with conductive members extending through the second layer to connect to the less dense pattern of circuitized substrate conductors.Type: ApplicationFiled: November 30, 2009Publication date: June 2, 2011Inventors: Timothy Antesberger, Frank D. Egitto, Voya R. Markovich, William E. Wilson
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Publication number: 20110126408Abstract: A method of making an electronic package designed for interconnecting high density patterns of conductors of an electronic device (e.g., semiconductor chip) and less dense patterns of conductors of hosting circuitized substrates (e.g., chip carriers, PCBs). In one embodiment, the method includes bonding a chip to a single dielectric layer, forming a high density pattern of conductors on one surface of the layer, forming openings in the layer and then depositing metallurgy to form a desired circuit pattern which is then adapted for engaging and being electrically coupled to a corresponding pattern on yet another hosting substrate. According to another embodiment of the invention, an electronic package using a dual layered interposer is provided. Also provided are methods of making circuitized substrate assemblies using the electronic packages made using the invention's teachings.Type: ApplicationFiled: December 1, 2009Publication date: June 2, 2011Inventors: Timothy Antesberger, Frank D. Egitto, Voya R. Markovich, William E. Wilson
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Patent number: 7163847Abstract: A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, including the commoning bar and connected parts. The laser may also be used to expose selected ones of the circuit's other parts, including various pads used to accommodate a wirebond (from a chip) and also solder balls for eventual placement of the substrate on a larger circuit board.Type: GrantFiled: October 26, 2005Date of Patent: January 16, 2007Assignee: Endicott Interconnect Technologies, Inc.Inventors: Timothy Antesberger, James W. Fuller, Jr., John J. Konrad, John Kresge, Stephen Krasniak, Timothy L. Wells
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Patent number: 7091066Abstract: A method of making a circuitized substrate in which a commoning bar, used during the plating of the circuitry on the substrate and coupled to a second set of conductors which in turn are coupled to a first set of conductors, is terminated from the second set of conductors.Type: GrantFiled: October 27, 2005Date of Patent: August 15, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: Timothy Antesberger, James W. Fuller, Jr., John J. Konrad, John Kresge, Stephen Krasniak, Timothy L. Wells
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Patent number: 7084014Abstract: A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, including the commoning bar and connected parts. The laser may also be used to expose selected ones of the circuit's other parts, including various pads used to accommodate a wirebond (from a chip) and also solder balls for eventual placement of the substrate on a larger circuit board.Type: GrantFiled: October 7, 2003Date of Patent: August 1, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: Timothy Antesberger, James W. Fuller, Jr., John J. Konrad, John Kresge, Stephen Krasniak, Timothy L. Wells
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Publication number: 20060046462Abstract: A method of making a circuitized substrate in which a commoning bar, used during the plating of the circuitry on the substrate and coupled to a second set of conductors which in turn are coupled to a first set of conductors, is terminated from the second set of conductors.Type: ApplicationFiled: October 27, 2005Publication date: March 2, 2006Applicant: Endicott Interconnect Technologies, Inc.Inventors: Timothy Antesberger, James Fuller, John Konrad, John Kresge, Stephen Krasniak, Timothy Wells
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Publication number: 20060040426Abstract: A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, including the commoning bar and connected parts. The laser may also be used to expose selected ones of the circuit's other parts, including various pads used to accommodate a wirebond (from a chip) and also solder balls for eventual placement of the substrate on a larger circuit board.Type: ApplicationFiled: October 26, 2005Publication date: February 23, 2006Applicant: Endicott Interconnect Technologies, Inc.Inventors: Timothy Antesberger, James Fuller, John Konrad, John Kresge, Stephen Krasniak, Timothy Wells
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Publication number: 20050224167Abstract: A method of removing selected portions of material from a base material using a plurality of different depth cuts (e.g., using laser cutting) such that apertured sections (or segments) are expeditiously removed for eventual use with another component or otherwise. In one example, the segmented section so removed can be used to bond various elements of an electronic package which in turn can then be positioned and used within an information handling system such as a computer, server, mainframe, etc.Type: ApplicationFiled: June 13, 2005Publication date: October 13, 2005Applicant: Endicott Interconnect Technologies, Inc.Inventors: Timothy Antesberger, John Kresge
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Publication number: 20050074924Abstract: A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, including the commoning bar and connected parts. The laser may also be used to expose selected ones of the circuit's other parts, including various pads used to accommodate a wirebond (from a chip) and also solder balls for eventual placement of the substrate on a larger circuit board.Type: ApplicationFiled: October 7, 2003Publication date: April 7, 2005Applicant: Endicott Interconnect Technologies, Inc.Inventors: Timothy Antesberger, James Fuller, John Konrad, John Kresge, Stephen Krasniak, Timothy Wells