Patents by Inventor Timothy Arthur Valade

Timothy Arthur Valade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for producing a transistor gate with sub-photolithographic dimensions
    Patent number: 8211760
    Abstract: A method of fabricating a semiconductor device is disclosed. The method comprises patterning a photoresist over a compound semiconductor substrate; reducing a width of the photoresist; forming a hardmask over the substrate and not over the photoresist; removing the photoresist; etching to form and opening down to the substrate; forming a gate in the opening; and removing the hardmask except beneath the gate.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: July 3, 2012
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Nathan Ray Perkins, Timothy Arthur Valade, Albert William Wang
  • METHOD FOR PRODUCING A TRANSISTOR GATE WITH SUB-PHOTOLITHOGRAPHIC DIMENSIONS
    Publication number: 20110250743
    Abstract: Methods of fabricating compound semiconductor devices are described.
    Type: Application
    Filed: April 12, 2011
    Publication date: October 13, 2011
    Applicant: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Nathan Ray PERKINS, Timothy Arthur VALADE, Albert William WANG
  • Method for producing a transistor gate with sub-photolithographic dimensions
    Patent number: 7947545
    Abstract: A method of fabricating a semiconductor device, the method comprises forming a mask layer over a compound semiconductor substrate; and patterning a photoresist over the mask layer. The method comprises etching a portion of the mask layer beneath the photoresist; forming a hardmask over the substrate and not over the mask layer; removing the mask layer; etching to form and opening down to the substrate; and forming a gate in the opening.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 24, 2011
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Nathan Ray Perkins, Timothy Arthur Valade, Albert William Wang
  • METHOD FOR PRODUCING A TRANSISTOR GATE WITH SUB-PHOTOLITHOGRAPHIC DIMENSIONS
    Publication number: 20090111253
    Abstract: Methods of fabricating compound semiconductor devices are described.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 30, 2009
    Inventors: Nathan Ray Perkins, Timothy Arthur Valade, Albert William Wang