Abstract: A fault tolerant processing system including a prediction RAM employs a Lock Step Compare routine. The method developed allows the processing system to recover from single event upsets. In initialization, the branch prediction RAM is set to a known value. An engineering balance is achieved by adding logic to detect a branch RAM error and incurring the delay of re-initializing the entire RAM only when a RAM error has been detected.

Abstract: A fault-tolerant computer system having shadow registers for storing the contents of a primary array into a shadow array at the completion of a stored instruction execution. This is accomplished in one clock cycle with all registers being shadowed simultaneously. During rollback of execution steps for a checkpoint retry, the shadow register files provide a signal cycle unload of the shadow array into the primary array. LSSD latches are used in the shadow register file.

Abstract: A computer memory system having partitioned page address for instructions and operands. The partitioning scheme for the virtual addressing memory minimizes the delay between the translation logic and the page translation RAMs. Computer processor performance is delayed by only a single clock cycle by the sharing of the memory address bus control between two address processors.

Abstract: A data processing system includes branch prediction apparatus for storing branch data in a branch prediction RAM after each branch has occurred. The RAM interfaces with branch logic means which tracks whether a branch is in progress and if a branch was guessed. An operational code compression means forms each instruction into a new operation code of lesser bits and embeds a guess bit into the new operational code. Control means decode the compressed operational code as an input to an instruction execution unit whereby conditional branch occurs based on the guess bit provided a branch instruction is not in progress in the system.

Abstract: The parity generation circuit which is disclosed takes advantage of a property of the parity of a number before and after it has been incremented. This is characterized as the parity toggle property and it allows parity generation to be done on the most significant bits of an adder before the carry input to these most significant bits has been generated from the least significant bit portion of the sum produced by the adder. The final parity for the entire sum output of the addition process is adjusted quickly when the carry into the most significant bits of the sum becomes available from the least significant bit portion of the sum output. The parity toggle property of the invention allows for the quick adjustment of the parity without incurring the undue delay of waiting for the production of the carry output from the low order sum before commencing computations with the high order sum.