Abstract: A computer-implemented method, system, and computer program product for limiting the effects of uncorrected hard errors. A soft error is detected in the least recently used (LRU) vector. A group at the tier of the LRU vector subject to the error is then recorded. A counter tracking the number of soft errors involving the group at the tier of the LRU vector subject to the soft error is updated (e.g., increased by a value of 1). If the value of the counter exceeds a threshold value, then such a soft error is deemed to be treated as a hard error. In such a situation, an error correction process is implemented for only the affected location of the LRU vector subject to the soft error. The target way is then set to include the most recently used data item in the non-errant associated groups of the LRU vector.

Abstract: implemented method, system, and computer program product for limiting the effects of uncorrected hard errors. A soft error is detected in the least recently used (LRU) vector. A group at the tier of the LRU vector subject to the error is then recorded. A counter tracking the number of soft errors involving the group at the tier of the LRU vector subject to the soft error is updated (e.g., increased by a value of 1). If the value of the counter exceeds a threshold value, then such a soft error is deemed to be treated as a hard error. In such a situation, an error correction process is implemented for only the affected location of the LRU vector subject to the soft error. The target way is then set to include the most recently used data item in the non-errant associated groups of the LRU vector.

Abstract: Embodiments are for processor cross-core cache line contention management. A computer-implemented method includes sending a cross-invalidate command to one or more caches based on receiving a cache state change request for a cache line in a symmetric multiprocessing system and determining a retry delay based on receiving a cross-invalidate reject response from at least one of the one or more caches. The computer-implemented method also includes waiting until a retry delay period associated with the retry delay has elapsed to resend the cross-invalidate command to the one or more caches and granting the cache state change request for the cache line based on receiving a cross-invalidate accept response from the one or more caches.

Abstract: An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a memory array including a plurality of memory macros including at least first and second memory macros. Each of the plurality of memory macros includes multiple partial arrays and a shared macro controller configured to control read and write access to the multiple partial arrays. The memory array also includes spare access control logic configured to direct an access to a first partial array in the first memory macro to a second partial array in the second memory macro.

Abstract: A lower-level cache managing cross-core invalidation (XI) snapshots in a shared-memory multiprocessing system, wherein the management of XI snapshots reduces an amount of required snapshots while allowing shared lower-level caches, comprising: the lower-level cache maintaining respective response sync state for at least one processor in a plurality of processors signifying that a line may have been changed by another processor since last fetched by a requesting processor.

Abstract: Techniques and apparatus for performing real-time tracking and reporting of snoop activity within a data processing system are described. An example technique includes performing a local snoop operation for multiple processors within a cluster. A snoop tracing message with information associated with the local snoop operation is generated upon determining that the local snoop operation is successful. The snoop tracing message is transmitted to a storage device. Another example technique includes determining a location in memory of a computing system where a fetch request resolves. Information indicating the location in memory of the computing system where the fetch request resolves is encoded within a fetch response. The fetch response is transmitted to a processor. One or more counters within the processor that are used to track snoop activity are incremented based on the encoded information.

Abstract: Castout handling in a distributed cache topology, including: detecting, by a first cache of a plurality of caches, a cache miss; providing, by the first cache to each other cache of the plurality of caches, a message comprising: data indicating a cache address corresponding to the cache miss; and data indicating a cache line to be evicted.

Abstract: Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

Abstract: A network of hang avoidance controllers and components which provide layer or scope based hang avoidance mechanisms in a distributed computing system is described. The detection of hang avoidance conditions and activation of the hang avoidance mechanisms are implemented on various limited scopes in the computing system, which prevent unnecessary system wide interruptions to avoid potential hangs in the system.

Abstract: A node of the computing environment obtains an exclusive fetch request of a cache line shared by, at least, the node and a manager node of the computing environment. The exclusive fetch request includes a state indication regarding processing of the exclusive fetch request by the manager node. The node processes the exclusive fetch request, based on the state indication included with the exclusive fetch request regarding processing of the exclusive fetch request by the manager node.

Abstract: A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.

Abstract: Embodiments are for processor cross-core cache line contention management. A computer-implemented method includes sending a cross-invalidate command to one or more caches based on receiving a cache state change request for a cache line in a symmetric multiprocessing system and determining a retry delay based on receiving a cross-invalidate reject response from at least one of the one or more caches. The computer-implemented method also includes waiting until a retry delay period associated with the retry delay has elapsed to resend the cross-invalidate command to the one or more caches and granting the cache state change request for the cache line based on receiving a cross-invalidate accept response from the one or more caches.

Abstract: A lower-level cache managing cross-core invalidation (XI) snapshots in a shared-memory multiprocessing system, wherein the management of XI snapshots reduces an amount of required snapshots while allowing shared lower-level caches, comprising: the lower-level cache maintaining respective response sync state for at least one processor in a plurality of processors signifying that a line may have been changed by another processor since last fetched by a requesting processor.

Abstract: Aspects include using a shadow copy of a level 1 (L1) cache in a cache hierarchy. A method includes maintaining the shadow copy of the L1 cache in the cache hierarchy. The maintaining includes updating the shadow copy of the L1 cache with memory content changes to the L1 cache a number of pipeline cycles after the L1 cache is updated with the memory content changes.

Abstract: A computer-implemented method is provided. The method includes determining whether a rejection of a request is required and determining whether the request is software forward progress (SFP)-likely or SFP-unlikely upon determining that the rejection of the request is required. The method also includes executing a first pseudo random decision to set or not set a requested state of the request in an event the request is SFP-likely or SFP-unlikely, respectively, and rejecting the request following execution of the second pseudo random decision.

Abstract: A method for managing designated authority status in a cache line includes identifying an initial designated authority (DA) member cache for a cache line, transferring DA status from the initial DA member cache to a new DA member cache, determining whether the new DA member cache is active, indicating a final state of the initial DA cache responsive to determining that the new DA member cache is active, and overriding a DA state in a cache control structure in a directory. A method for managing cache accesses during a designated authority transfer includes receiving a designated authority (DA) status transfer request, receiving an indication that a first cache will invalidate its copy of the cache line, allowing a second cache to assume DA status for the cache line, and denying access to the first cache's copy of the cache line until invalidation by the first cache is complete.

Abstract: A primary controller has authority of a cache line associated with a fetch and manages a second cache line request from a different and non-associated secondary requesting entity. A secondary controller, associated with the secondary requesting entity, is granted authority of the cache line and further manages multiple subsequent simultaneous or overlapping requests for the cache line from different non-associated subsequent requesting entities by maintaining authority of the cache line, by granting read-only access to the cache line to respective subsequent controllers, each associated with a different subsequent requesting entity, and by passing a non-authority token to each of the respective subsequent controllers.

Abstract: A method and a computer system for core recovery management are provided. A first operation signal is generated via a first hardware agent. The first operation signal indicates that the first hardware agent is processing an operation requested by a first processor core. The first processor core receives a first extend fence signal based on the generated first operation signal. As long as the first extend fence signal is received via the first processor core, the first processor core is kept in a fenced state for core recovery.

Abstract: Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

Abstract: Castout handling in a distributed cache topology, including: detecting, by a first cache of a plurality of caches, a cache miss; providing, by the first cache to each other cache of the plurality of caches, a message comprising: data indicating a cache address corresponding to the cache miss; and data indicating a cache line to be evicted.