Abstract: An efficient method and apparatus for characterizing circuit devices is disclosed. In one embodiment, multiple test patterns for testing a circuit device are stored in a tester. Each test pattern includes both test data and control data that defines at least in part a sweep point at which the circuit device is tested. Thus, the tester can generate stimulus vectors for multiple sweep points without requiring control system intervention. Pass/fail indicators, each of which represents pass/fail results associated with a sweep point, are derived from the test results and stored in a Fail Capture Memory. A pass/fail boundary of the DUT can be determined from the contents of the Fail Capture Memory.

Abstract: Error detection mechanisms for devices that have multilevel signal interfaces test multilevel signals of an interface with a binary test apparatus. The error detection mechanisms include converting between multilevel signals of the interface and binary signals of the test apparatus. The error detection mechanisms also include repeated transmission of multilevel signals stored in a memory of a device having a multilevel signal interface for detection by the test apparatus at different binary levels.

Abstract: An efficient method and apparatus for characterizing circuit devices is disclosed. In one embodiment, multiple test patterns for testing a circuit device are stored in a tester. Each test pattern includes both test data and control data that defines at least in part a sweep point at which the circuit device is tested. Thus, the tester can generate stimulus vectors for multiple sweep points without requiring control system intervention. Pass/fail indicators, each of which represents pass/fail results associated with a sweep point, are derived from the test results and stored in a Fail Capture Memory. A pass/fail boundary of the DUT can be determined from the contents of the Fail Capture Memory.

Abstract: An efficient method and apparatus for characterizing circuit devices is disclosed. In one embodiment, multiple test patterns for testing a circuit device are stored in a tester. Each test pattern includes both test data and control data that defines at least in part a sweep point at which the circuit device is tested. Thus, the tester can generate stimulus vectors for multiple sweep points without requiring control system intervention. Pass/fail indicators, each of which represents pass/fail results associated with a sweep point, are derived from the test results and stored in a Fail Capture Memory. A pass/fail boundary of the DUT can be determined from the contents of the Fail Capture Memory.

Abstract: Error detection mechanisms for devices that have multilevel signal interfaces test multilevel signals of an interface with a binary test apparatus. The error detection mechanisms include converting between multilevel signals of the interface and binary signals of the test apparatus. The error detection mechanisms also include repeated transmission of multilevel signals stored in a memory of a device having a multilevel signal interface for detection by the test apparatus at different binary levels.