Abstract: A wireless hoist system including a first hoist device having a first motor and a first wireless transceiver and a second hoist device having a second motor and a second wireless transceiver. The wireless hoist system includes a controller in wireless communication with the first wireless transceiver and the second wireless. The controller is configured to receive a user input and determine a first operation parameter and a second operation parameter based on the user input. The controller is also configured to provide, wirelessly, a first control signal indicative of the first operation parameter to the first hoist device and provide, wirelessly, a second control signal indicative of the second operation parameter to the second hoist device. The first hoist device operates based on the first control signal and the second hoist device operates based on the second control signal.

Abstract: Described herein are systems and methods that eliminate the need for costly and complex switching networks for routing channelized data between antenna elements and beamformers. In one aspect, a beamforming system comprises a beamformer for each antenna element of an antenna array, in which the beamformers for the different antenna elements are arranged in parallel. The beamforming system also comprises a combiner that combines the outputs of the beamformers into a single beam. In one aspect, the beamformers of antenna elements that do not contribute to a desired beam output zeros to the combiner, which when added to the subbeams of the other beamformers have no affect of the final beam. In another aspect, operations (e.g., multiplication, memory reads) of each beamformer that does not contribute to a desired beam may be turned off to conserve power.

Abstract: A method for detecting and correcting bit errors. The method includes the steps of receiving original data, partitioning the memory storage into a first portion and a second portion, storing the original data in the first portion of the memory buffer, modifying the original data into modified data, storing the modified data in the second portion of the memory buffer, comparing the original data with the modified data, combining the original data and the modified data to create a final data stream, and outputting the final data stream. The method may further include the step of calculating and storing parity data.

Abstract: A system for remotely synchronizing a majority voter circuit. The system comprises a first processor for generating a data packet and a synchronization pulse wherein the synchronization pulse indicates a predetermined bit location in the data packet. The system further comprises a plurality of second processors communicatively coupled to the first processor. Each of the plurality of second processors has a register, and each of the plurality of second processors receives the data packet and the synchronization pulse, and stores the data packet and the synchronization pulse in its respective register. A voting processor is communicatively coupled to each of the plurality of second processors. The voting processor receives at least a portion of the data packet from each of the plurality of processors, and utilizes the synchronization pulse to align each of the received portions of the data packets, according to the synchronization pulse prior to voting.

Abstract: Described herein are systems and methods that eliminate the need for costly and complex switching networks for routing channelized data between antenna elements and beamformers. In one aspect, a beamforming system comprises a beamformer for each antenna element of an antenna array, in which the beamformers for the different antenna elements are arranged in parallel. The beamforming system also comprises a combiner that combines the outputs of the beamformers into a single beam. In one aspect, the beamformers of antenna elements that do not contribute to a desired beam output zeros to the combiner, which when added to the subbeams of the other beamformers have no affect of the final beam. In another aspect, operations (e.g., multiplication, memory reads) of each beamformer that does not contribute to a desired beam may be turned off to conserve power.

Abstract: Automatic fault recovery of upsets in a memory controller are provided to minimize data loss. In addition to memory control, the present invention allows for the incorporation of majority voting circuits with integrated alignment between three voted data streams. The memory array is divided into two basic components: (1) the write side (data in); and (2) the read side (data out). Each of these components has a separate memory address counter. The write counter is loaded into a holding register during a synchronization period. After determining the validity of the write cycle for fault tolerance and setting data latency for pipelining, the read counter is loaded with the write counter value. The reading of the memory array commences at the counter value that was stored in the read counter, which is the same as the original write counter value.