Patents by Inventor Timothy C. Krywanczyk

Timothy C. Krywanczyk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7572739
    Abstract: A semiconductor structure fabrication method for removing a tape physically attached to a device side of the semiconductor substrate by an adhesive layer of the tape, wherein the adhesive layer comprises an adhesive material. The method includes the step of submerging the tape in a liquid chemical comprising monoethanolamine or an alkanolamine for a pre-specified period of time sufficient to allow for a separation of the tape from the semiconductor substrate without damaging devices on the semiconductor substrate.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: August 11, 2009
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Codding, Timothy C Krywanczyk, Steven G. Perrotte, Jason P. Ritter
  • Publication number: 20090084499
    Abstract: A method for preventing edge chipping and cracking damage encountered by semiconductor chips in a die picking operation during separation from an adhesive sheet. Also provided is a device for preventing potential edge chipping and cracking damage encountered by a semiconductor chip during die picking processes.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James R. Johnson, Timothy C. Krywanczyk, Matthew R. Whalen
  • Patent number: 7498236
    Abstract: Disclosed are a method of and system for fabricating a semiconductor wafer. The method comprises the steps of providing a silicon wafer having a front side an a back side, building an integrated circuit on the front side of the wafer, and thereafter removing substrate from the back side of the silicon wafer. The building step includes the steps of forming a desired structure in the wafer, and forming an end structure in the wafer, said end structure extending to a greater depth, toward the back side of the wafer, than the desired structure. Also, the removing step includes the step of removing said substrate only to the end structure, whereby no part of the desired structure is removed during the removing step.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: March 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Codding, Timothy C. Krywanczyk, Edmund J. Sprogis
  • Patent number: 7387911
    Abstract: A thermally conductive protective film or layer is applied to the backside surface of a semiconductor wafer prior to a subsequent dicing operation performed on the wafer to singulate the wafer into diced semiconductor chips, during which the thin thermally conductive film minimizes and prevents chipping and cracking damage to the wafer and diced chips. During subsequent electrical operation of a diced chip, the thin thermally conductive film functions as a thermal conductor to dissipate and conduct away to a heat sink any heat generated during operation of the chip.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: June 17, 2008
    Assignee: International Business Machines Corporation
    Inventors: David M Audette, Steven R. Codding, Timothy C. Krywanczyk, Brian J. Thibault, Matthew R. Whalen
  • Publication number: 20080138989
    Abstract: Disclosed are embodiments of a method of removing patterned circuit structures from the surface of a semiconductor wafer. The method embodiments comprise blasting the surface of the semiconductor wafer with particles so as to remove substantially all of the patterned circuit structures. The blasting process is followed by one or more grinding, polishing and/or cleaning processes to remove any remaining circuit structures, to remove any lattice damage and/or to achieve a desired smoothness across the surface of the semiconductor wafer.
    Type: Application
    Filed: February 15, 2008
    Publication date: June 12, 2008
    Inventors: Steven R. Codding, David Domina, James L. Hardy, Timothy C. Krywanczyk
  • Publication number: 20080124896
    Abstract: Disclosed are a method of and system for fabricating a semiconductor wafer. The method comprises the steps of providing a silicon wafer having a front side an a back side, building an integrated circuit on the front side of the wafer, and thereafter removing substrate from the back side of the silicon wafer. The building step includes the steps of forming a desired structure in the wafer, and forming an end structure in the wafer, said end structure extending to a greater depth, toward the back side of the wafer, than the desired structure. Also, the removing step includes the step of removing said substrate only to the end structure, whereby no part of the desired structure is removed during the removing step.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 29, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Codding, Timothy C. Krywanczyk, Edmund J. Sprogis
  • Publication number: 20080113458
    Abstract: A method for inspecting a semiconductor wafer fabricated for image sensing operation that has had a transparent protective tape layer applied to a front or active wafer surface. The method includes quantifying chip defects in the image sensor wafer that lie under the protective layer using automatic disposition equipment.
    Type: Application
    Filed: November 15, 2006
    Publication date: May 15, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy C. Krywanczyk, Timothy E. Neary, Erik M. Probstfield
  • Publication number: 20080113456
    Abstract: A method for protecting a semiconductor wafer fabricated for image sensing operation from contamination and/or physical damage to a front wafer surface during post-fabrication processing. The method includes applying a protective tape layer on the front surface of the semiconductor wafer in order to protect active light sensors fabricated thereon.
    Type: Application
    Filed: November 15, 2006
    Publication date: May 15, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Codding, Timothy C. Krywanczyk, Robert K. Leidy
  • Patent number: 7348216
    Abstract: A method for the removal of residual UV radiation-sensitive adhesive from the surfaces of semiconductor wafers, remaining thereon from protective UV radiation-sensitive tapes which were stripped from the semiconductor wafers. Moreover, provided is an arrangement for implementing the removal of residual sensitive adhesive, which remain from tapes employed as protective layers on semiconductor wafers, particularly wafers having surfaces including C4 connections.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: March 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Codding, Timothy C. Krywanczyk, Edmund J. Sprogis, Jocelyn Sylvestre, Matthew R. Whalen
  • Patent number: 7288465
    Abstract: There is provided a method for making a wafer comprising the steps of providing a substrate having a first surface, an opposite second surface, and at least one side edge defining a thickness of the substrate, the at least one side edge having a first peripheral region and a second peripheral region adjacent to the first peripheral region. The method includes applying a fluid to the first surface and the first peripheral region of the at least one side edge and removing the opposite second surface and the second peripheral region of the at least one side edge to form a third surface. A semiconductor chip made from the method for making the wafer is also provided.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: October 30, 2007
    Assignee: International Business Machines Corpoartion
    Inventors: Allan D. Abrams, Donald W. Brouillette, Joseph D. Danaher, Timothy C. Krywanczyk, Rene A. Lamothe, Ivan J. Stone, Matthew R. Whalen
  • Patent number: 7135124
    Abstract: In accordance with the foregoing objects and advantages, the present invention provides a fabrication device that may be used during the grinding operation of the fabrication process. The fabrication device comprises a socket plate that includes a plurality of cavities formed therein that correspond in position and number to the solder (or other conductive material) bumps formed on the front surface of a product wafer.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: November 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Timothy C. Krywanczyk, Edmund J. Sprogis
  • Patent number: 7074715
    Abstract: A structure and method of formation. The substrate has front and back surfaces on opposite sides of the substrate. The substrate has a backside portion extending from the back surface to a second depth into the substrate as measured from the front surface. At least one via is formed in the substrate and extends from the front surface to a via depth into the substrate. The via depth is specific to each via. The via depth of each via is less than an initial thickness of the substrate. The second depth does not exceed the minimum via depth of the via depths. Organic material (e.g., photoresist) is inserted into each via. The organic material is subsequently covered with a tape, followed by removal of the backside portion of the substrate. The tape is subsequently removed from the organic material, followed by removal of the organic material from each via.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: July 11, 2006
    Assignee: International Business Machines Corporation
    Inventors: Donald W. Brouillette, Joseph D. Danaher, Timothy C. Krywanczyk, Amye L. Wells
  • Patent number: 7025891
    Abstract: A method of treating a molybdenum (moly) mask used in a C4 process to pattern C4 contacts. The moly mask has a wafer side which contacts a wafer during the C4 process and has a rough surface that includes spikes/projections of moly. The moly mask also has a non wafer side and a plurality of holes extending through the mask to pattern C4 contacts in the C4 process. An adhesive layer, such as an adhesive tape, is applied to the non wafer side of the moly mask, to enable a polishing tool to pull a vacuum on the non wafer side of the moly mask in spite of the presence of the holes to secure the moly mask during a subsequent polishing step. The tape also functions as a cushion so that defects on the non wafer side of the moly mask do not replicate through the moly mask to the polished wafer side of the moly mask.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: April 11, 2006
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Codding, Timothy C. Krywanczyk, Joseph D. Danaher, John C. Malinowski, James R. Palmer, Melvin T. Kelly, Caitlin W. Weinstein, Wolfgang Sauter
  • Patent number: 7001827
    Abstract: There is provided a method for making a wafer including the steps of providing a substrate having a first surface, an opposite second surface, and at least one side edge defining a thickness of the substrate, the at least one side edge having a first peripheral region and a second peripheral region adjacent to the first peripheral region. The method includes applying a fluid to the first surface and the first peripheral region of the at least one side edge and removing the opposite second surface and the second peripheral region of the at least one side edge to form a third surface. A semiconductor chip made from the method for making the wafer is also provided.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: February 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Allan D. Abrams, Donald W. Brouillette, Joseph D. Danaher, Timothy C. Krywanczyk, Rene A. Lamothe, Ivan J. Stone, Matthew R. Whalen
  • Patent number: 6888223
    Abstract: A structure and method of formation. The substrate has front and back surfaces on opposite sides of the substrate. The substrate has a backside portion extending from the back surface to a second depth into the substrate as measured from the front surface. At least one via is formed in the substrate and extends from the front surface to a via depth into the substrate. The via depth is specific to each via. The via depth of each via is less than an initial thickness of the substrate. The second depth does not exceed the minimum via depth of the via depths. Organic material (e.g., photoresist) is inserted into each via. The organic material is subsequently covered with a tape, followed by removal of the backside portion of the substrate. The tape is subsequently removed from the organic material, followed by removal of the organic material from each via.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: May 3, 2005
    Assignee: International Business Machines Corporation
    Inventors: Donald W. Brouillette, Joseph D. Danaher, Timothy C. Krywanczyk, Amye L. Wells
  • Publication number: 20040209444
    Abstract: There is provided a method for making a wafer comprising the steps of providing a substrate having a first surface, an opposite second surface, and at least one side edge defining a thickness of the substrate, the at least one side edge having a first peripheral region and a second peripheral region adjacent to the first peripheral region. The method includes applying a fluid to the first surface and the first peripheral region of the at least one side edge and removing the opposite second surface and the second peripheral region of the at least one side edge to form a third surface. A semiconductor chip made from the method for making the wafer is also provided.
    Type: Application
    Filed: April 15, 2003
    Publication date: October 21, 2004
    Applicant: International Business Machines Corporation
    Inventors: Allan D. Abrams, Donald W. Brouillette, Joseph D. Danaher, Timothy C. Krywanczyk, Rene A. Lamothe, Ivan J. Stone, Matthew R. Whalen
  • Publication number: 20040209443
    Abstract: An improved method of dicing a semiconductor wafer which substantially reduces or eliminates corrosion of copper-containing, aluminum bonding pads. The method involves continuously contacting the bonding pads with deionized water and an effective amount of a copper corrosion inhibiting agent, most preferably benzotriazole. Also disclosed, is an improved apparatus for dicing a wafer, in which a copper corrosion inhibiting agent is included in the cooling system for cooling the dicing blade.
    Type: Application
    Filed: April 21, 2003
    Publication date: October 21, 2004
    Applicant: International Business Machines Corporation
    Inventors: Robert R. Cadieux, Scott A. Estes, Timothy C. Krywanczyk
  • Publication number: 20040198021
    Abstract: A structure and method of formation. The substrate has front and back surfaces on opposite sides of the substrate. The substrate has a backside portion extending from the back surface to a second depth into the substrate as measured from the front surface. At least one via is formed in the substrate and extends from the front surface to a via depth into the substrate. The via depth is specific to each via. The via depth of each via is less than an initial thickness of the substrate. The second depth does not exceed the minimum via depth of the via depths. Organic material (e.g., photoresist) is inserted into each via. The organic material is subsequently covered with a tape, followed by removal of the backside portion of the substrate. The tape is subsequently removed from the organic material, followed by removal of the organic material from each via.
    Type: Application
    Filed: April 1, 2003
    Publication date: October 7, 2004
    Inventors: Donald W. Brouillette, Joseph D. Danaher, Timothy C. Krywanczyk, Amye L. Wells
  • Patent number: 6599173
    Abstract: A CMP slurry for and method of polishing a semiconductor wafer during formation of metal interconnects are disclosed. The present invention utilizes a first slurry comprising a first oxidizer, preferably ferric nitrate, to remove the excess metal of the metal interconnect but which leaves the metal residues on the surface of the wafer. A second slurry comprising another oxidizer, preferably potassium iodate solution, having a greater affinity to both the metal residue and the liner material than the underlying dielectric is used to remove the metal residue and liner material with significantly reduced scratching of the underlying dielectric. The more robust metal interconnects formed utilizing the present invention is effective in lowering the overall resistance of a wafer, reducing the number of shorts, and provides greater protection of the underlying dielectric. Overpolishing of the wafer and its associated problems are avoided.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: July 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Jose L. Cruz, Cuc K. Huynh, Timothy C. Krywanczyk, Douglas K. Sturtevant
  • Patent number: 6455434
    Abstract: The present invention provides a method of preventing the build-up of polishing material within low areas of a substrate during polishing. Following the blanket deposition of a first layer, a selectively removable material is deposited over the first layer, wherein the selectively removable material fills the low areas. A surface of the substrate is polished removing the excess first layer and selectively removable material from the surface, leaving the first layer and selectively removable material within the low area. Following polishing, the selectively removable material is removed from the low areas prior to the deposition of a second layer.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: September 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chad R. Binkerd, Jose L. Cruz, Timothy C. Krywanczyk, Brian D. Pfeifer, Rosemary A. Previti-Kelly, Patricia Schink, Amye L. Wells