Abstract: A contact member for thermocompression bonding in integrated circuit packaging has on a conductor end a uniform texture deformable layer with a hardness value in the range of that of soft gold which is approximately 90 on the Knoop scale and with a rough surface morphology having ridges with approximately 1 micrometer modulation frequency and a depth between ridges of from 1/4 to 1/2 that of the average integrated circuit pad. The deformable layer is produced by plating gold in a strong electronegative plating bath within a range of 0.03 to 0.05 mA/sq.mm. current density. Plating apparatus, for plating different areas, with different electronegative conditions, with separate independently powered anodes, is provided.

Abstract: A semiconductor chip carrying integrated circuits has lead lines terminating in conductive terminal pads exposed to the exterior through openings in a passivation layer. The pads include pedestals or bumps extending up from them. Each of the pedestals includes a thin metallic adhesion layer deposited on the pad. A thick metallic layer of aluminum or an alloy of aluminum is deposited upon said thin metallic adhesion layer. The thick metallic layer includes at least one metal selected from the group consisting of aluminum, aluminum plus a small percentage of Cu, Ni, Si, or Fe. Several other alternative metals can be added to aluminum to form an alloy. The thick metallic layer forms the bulk of the height of the pedestal. An adhesion layer is deposited on the bump of aluminum composed of a thin film of titanium or chromium. A barrier layer is deposited on the adhesion layer composed of copper, nickel, platinum, palladium or cobalt.

Abstract: A contact member for thermocompression bonding in integrated circuit packaging has on a conductor end a uniform texture deformable layer with a hardness value in the range of that of soft gold which is approximately 90 on the Knoop scale and with a rough surface morphology having ridges with approximately 1 micrometer modulation frequency and a depth between ridges of from 1/4 to 1/2 that of the average integrated circuit pad. The deformable layer is produced by plating gold in a strong electronegative plating bath within a range of 0.03 to 0.05 mA/sq.cm. current density. Plating apparatus, for plating different areas, with different electronegative conditions, with separatre independently powered anodes, is provided.

Abstract: Electronic device packaging structures useful for electrically interconnecting an electronic device to a substrate. The structure contains at least two metallization layers with dielectric layers between adjacent to metallization layers. The dielectric layers can have variable thickness. Beam leads can project inwardly in cantilevered fashion over a central aperture through the dielectric layers. The inner ends of the beam leads lie substantially in one plane and can be bonded to contact pads on integrated circuit electronic devices. Beam leads can project outwardly from the metallization layers over outer edges of the dielectric layers for bonding to contact pads on a substrate. Signal leads on metallization layers can be symmetrically arranged between ground and voltage leads to provide optimal impedance properties. These structures are useful for tape automated bonding applications.

Abstract: A contact member for thermocompression bonding in integrated circuit packaging has on a conductor end a uniform texture deformable layer with a hardness value in the range of that of soft gold which is approximately 90 on the Knoop scale and with a rough surface morphology having ridges with approximately 1 micrometer modulation frequency and a depth between ridges of from 1/4 to 1/2 that of the average integrated circuit pad. The deformable layer is produced by plating gold in a strong electronegative plating bath within a range of 0.03 to 0.05 mA/sq.cm. current density. Plating apparatus, for plating different areas, with different electronegative conditions, with separate independently powered anodes, is provided.

Abstract: A TAB package comprises an elongated tape which has a plurality of sets of beam leads emplaced thereon and a plurality of electronic devices connected to the beam leads. At least a first beam lead of each set is connected to a common potential terminal on each device, and at least a second beam lead of each set is connected to a power terminal. A common potential bus is oriented along the elongated dimension of the tape and connects to the first beam leads, while a power bus is also oriented along the elongated dimension of the tape and is connected to the second beam leads. The application of power to the power bus and the simultaneous grounding of the common potential bus enables all electronic devices on the tape to be simultaneously energized and to be then subjected to an elevated temperature environment for static burn-in testing.

Abstract: An integrated circuit device package in which integrated circuit devices are mounted with active faces placed facing each other to form a double-device structure. Input/output terminals on the active faces of each device can be electrically interconnected by placing an interconnection means between the chips to electrically interconnect input/output terminals on the active faces of the first and second device. Beam leads, each having an inner and outer lead bond site, project outwardly from between the devices where each of the inner lead bond site is solderlessly bonded between conducting patterns on each device bonded. A series of double-device structures can be formed on a tape having a plurality of sets of beam lead patterns thereon. Each beam lead of each set having an inner and outer lead bond site, projects outwardly from between the double-device structure, the inner lead bond site being solderlessly bonded between conducting patterns on each device.

Abstract: Automated bonding of chips to tape and formation of bonding structures on Tape Automated Bonding (TAB) packaging structures are provided with bonding balls on the ends of beams leads of the TAB tape. Also balltape bonding balls are aligned on stacked TAB sheets and bonded together to form via interconnections through stacked balltape balls in multilayer, electronic packaging structures. Interconnection structures are provided for a universal chip connection laminate which can be applied between a chip and an MLC package. Area TAB tape, which comprises a modification of TAB tape provides balltape TAB connections by means of balltape bonds to areas within the interior of a chip whose leads are bonded in a TAB tape arrangement to the Inner Lead Bonds of the area tape.

Abstract: A method for forming a pattern in a metallic and/or ceramic substrate by laminating together the substrate which is in the green stage and a composite of a photosensitive material and a backing wherein the photosensitive material has been developed into the desired pattern, and then subjecting the substrate to elevated temperatures in order to cause sintering of the substrate and removal of the photosensitive material, thereby resulting in embedding of the pattern into the sintered substrate.

Abstract: A laminated capacitor is joined to the surface of a chip carrier for large scale integrated circuit chips. The capacitor lies adjacent to positions where chips are located. The capacitor includes a plurality of capacitor plates. The capacitor is bonded to the chip carrier with an array of solder bars comprising an elongated strip of metallic material. Each of the bars is connected to a set of the capacitor plates in the laminated capacitor by means of tab connections on the plates, whereby each of the plates is connected by a plurality of tabs to a plurality of the solder bars. Methods of fabrication of the laminated capacitor structure and solder bars are described.