Patents by Inventor Timothy Canepa
Timothy Canepa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11449431Abstract: A data storage device may consist of a non-volatile memory having rewritable in-place memory cells each with a read-write asymmetry. The non-volatile memory can store boot data that is subsequently loaded by a selection module of the data storage device. The selection module may bypass a memory buffer of the data storage device to load the boot data.Type: GrantFiled: May 30, 2017Date of Patent: September 20, 2022Inventors: Mark Ish, Timothy Canepa, David S. Ebsen
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Patent number: 10909051Abstract: Method and apparatus for managing a non-volatile memory (NVM). In some embodiments, a memory module has a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A controller is adapted to communicate commands and data to the MME circuit via an intervening data bus. The controller operates to reset the MME circuit by issuing a reset command to the MME circuit over the data bus, activating a decoupling circuit coupled between the data bus and a reference line at a reference voltage level to remove capacitance from the data bus resulting from the reset command, and subsequently sensing a voltage on the data bus. In some cases, multiple MME circuits and NVMs may be arranged on a plurality of flash dies which are concurrently reset by the controller.Type: GrantFiled: June 1, 2017Date of Patent: February 2, 2021Assignee: Seagate Technology LLCInventor: Timothy Canepa
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Patent number: 10754555Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.Type: GrantFiled: November 27, 2018Date of Patent: August 25, 2020Assignee: Seagate Technology LLCInventors: Timothy Canepa, Jeffrey Munsil, Jackson Ellis, Mark Ish
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Patent number: 10756895Abstract: Systems and methods for using encryption keys to manage data retention are described. In one embodiment, the systems and methods may include receiving data such as user data from a host of the storage drive, encrypting the data using an encryption key, writing the encrypted data to the storage drive, and retaining the encrypted data on the storage drive based at least in part on a validity of the encryption key.Type: GrantFiled: October 19, 2018Date of Patent: August 25, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Timothy Canepa, Ramdas Kachare
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Patent number: 10740251Abstract: The implementations described herein provide a hybrid drive with a storage capacity including solid-state drive (NAND) technology and hard disc drive (HDD) technology. A translation layer is stored in the solid-state drive and includes plurality of entries. Each entry of the plurality of entries corresponds to at least one logical data unit and includes a cache state indicating where the data corresponding to the logical data unit is located and whether the data is valid. The translation layer may be a multi-layer map that includes a sparse mapping scheme. In a sparse multi-layer map, entries are leaf entries or non-leaf entries. Leaf entries include a cache state for the corresponding logical data unit(s). Non-leaf entries may include a pointer to a lower level mapping for a plurality of logical data units.Type: GrantFiled: January 20, 2017Date of Patent: August 11, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Alex Tang, Leonid Baryudin, Timothy Canepa, Jackson Ellis
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Patent number: 10664168Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.Type: GrantFiled: November 27, 2018Date of Patent: May 26, 2020Assignee: Seagate Technology LLCInventors: Timothy Canepa, Stephen Hanna
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Patent number: 10635581Abstract: A garbage collection method comprises selecting one or blocks in a SSD of a hybrid drive for garbage collection; determining a state of data of the one or more selected blocks, wherein the state suggests a location and temperature of data; and executing a garbage collection efficiency and caching efficiency action on the data of the one or more selected blocks based on the determined state. The garbage collection process may utilize the state information provided by the cache layer of the hybrid drive to make decisions regarding data in the one or more selected blocks.Type: GrantFiled: January 20, 2017Date of Patent: April 28, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Alex Tang, Leonid Baryudin, Timothy Canepa, Mark Ish, Jackson Ellis
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Patent number: 10559376Abstract: A data storage device can have at least a buffer memory, a selection module, and a non-volatile memory. The buffer memory and non-volatile memory may consist of different types of memory while the non-volatile memory has one or more rewritable in-place memory cells. The buffer memory and non-volatile memory may each store data associated with a pending data request as directed by the selection module until a settle time of the rewritable in-place memory cell has expired.Type: GrantFiled: October 1, 2018Date of Patent: February 11, 2020Assignee: Seagate Technology LLCInventors: Timothy Canepa, Mark Ish, David S. Ebsen
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Patent number: 10430357Abstract: An apparatus to arbitrate data transfer between a computing host and a storage device across an interface includes a data transfer limiter configured to track an amount of data credits used by a data transfer across the interface and an amount of accrued data credits available to the interface. The apparatus further includes a data transfer arbiter configured to selectively disable the data transfer across the interface when the amount of data credits used by the data transfer across the interface exceeds a first threshold, and to selectively enable the data transfer across the interface when the amount of data credits used by the data transfer across the interface does not exceed a second threshold. The amount of accrued data credits reduces the amount of data credits used by the data transfer.Type: GrantFiled: February 20, 2018Date of Patent: October 1, 2019Assignee: Seagate Technology, LLCInventors: Ramdas Kachare, Timothy Canepa
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Patent number: 10303598Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller generally includes a processor, a cache and a hardware assist circuit. The processor may be configured to initiate a recycle operation by generation of a start index. The cache may be configured to buffer a first level of a map and less than all of a second level of the map. The hardware assist circuit may be configured to search through the first level or any portions of the second level of the map in the cache in response to the start index, and notify the processor in response to the search detecting one or more blocks in the memory that contain valid data to be recycled.Type: GrantFiled: June 29, 2016Date of Patent: May 28, 2019Assignee: Seagate Technology LLCInventors: Timothy Canepa, Leonid Baryudin, Stephen D. Hanna, Alex G. Tang
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Patent number: 10284231Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a solid-state non-volatile memory (NVM) has a total user data storage capacity and an overprovisioning (OP) level. A control circuit writes parity data sets to the NVM each having a plurality of code words and an outer code. The code words include inner codes at an inner code rate to detect and correct read errors in a user data payload. The outer code includes parity data at an outer code rate to detect and correct read errors in the code words. A code adjustment circuit increases the inner code rate to compensate for a measured parameter associated with the NVM, and decreases the outer code rate to maintain the data capacity and OP levels above selected thresholds.Type: GrantFiled: June 1, 2017Date of Patent: May 7, 2019Assignee: Seagate Technology, LLCInventor: Timothy Canepa
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Patent number: 10248330Abstract: A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.Type: GrantFiled: May 30, 2017Date of Patent: April 2, 2019Assignee: Seagate Technology LLCInventors: Jackson Ellis, Jeffrey Munsil, Timothy Canepa, Stephen Hanna
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Publication number: 20190096506Abstract: A data storage device can have at least a buffer memory, a selection module, and a non-volatile memory. The buffer memory and non-volatile memory may consist of different types of memory while the non-volatile memory has one or more rewritable in-place memory cells. The buffer memory and non-volatile memory may each store data associated with a pending data request as directed by the selection module until a settle time of the rewritable in-place memory cell has expired.Type: ApplicationFiled: October 1, 2018Publication date: March 28, 2019Inventors: Timothy Canepa, Mark Ish, David S. Ebsen
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Publication number: 20190095341Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.Type: ApplicationFiled: November 27, 2018Publication date: March 28, 2019Inventors: Timothy Canepa, Jeffrey Munsil, Jackson Ellis, Mark Ish
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Publication number: 20190095099Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.Type: ApplicationFiled: November 27, 2018Publication date: March 28, 2019Inventors: Timothy Canepa, Stephen Hanna
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Patent number: 10229000Abstract: Methods and structure for preventing lower page corruption in flash memory. One embodiment is a flash storage device that includes Multi-Level Cell (MLC) flash memory, Single-Level Cell (SLC) flash memory, and a controller coupled to the MLC flash memory and the SLC flash memory. The controller is configured to program host data to a lower page of the MLC flash memory, to generate an erasure code for the host data, and to store the erasure code in the SLC flash memory. The controller is also configured to detect an interrupted write operation to an upper page linked to the lower page, to retrieve the erasure code from the SLC flash memory, and to correct the host data of the lower page of the MLC flash memory using the erasure code.Type: GrantFiled: August 9, 2016Date of Patent: March 12, 2019Assignee: Seagate LLCInventors: Timothy Canepa, Stephen Hanna
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Patent number: 10229052Abstract: Method and apparatus for managing data such as in a flash memory. In some embodiments, a memory module electronics (MME) circuit writes groups of user data blocks to consecutive locations within a selected section of a non-volatile memory (NVM), and concurrently writes a directory map structure as a sequence of map entries distributed among the groups of user data blocks. Each map entry stores address information for the user data blocks in the associated group and a pointer to a subsequent map entry in the sequence. A control circuit accesses a first map entry in the sequence and uses the address information and pointer in the first map entry to locate the remaining map entries and the locations of the user data blocks in the respective groups. Lossless data compression may be applied to the groups prior to writing.Type: GrantFiled: May 31, 2017Date of Patent: March 12, 2019Assignee: Seagate Technology LLCInventors: Timothy Canepa, Ryan J. Goss, Stephen Hanna
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Publication number: 20190058583Abstract: Systems and methods for using encryption keys to manage data retention are described. In one embodiment, the systems and methods may include receiving data such as user data from a host of the storage drive, encrypting the data using an encryption key, writing the encrypted data to the storage drive, and retaining the encrypted data on the storage drive based at least in part on a validity of the encryption key.Type: ApplicationFiled: October 19, 2018Publication date: February 21, 2019Applicant: SEAGATE TECHNOLOGY LLCInventors: Timothy Canepa, Ramdas Kachare
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Publication number: 20180349148Abstract: A data storage device may consist of a non-volatile memory having rewritable in-place memory cells each with a read-write asymmetry. The non-volatile memory can store boot data that is subsequently loaded by a selection module of the data storage device. The selection module may bypass a memory buffer of the data storage device to load the boot data.Type: ApplicationFiled: May 30, 2017Publication date: December 6, 2018Inventors: Mark Ish, Timothy Canepa, David S. Ebsen
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Publication number: 20180349266Abstract: Method and apparatus for managing data such as in a flash memory. In some embodiments, a memory module electronics (MME) circuit writes groups of user data blocks to consecutive locations within a selected section of a non-volatile memory (NVM), and concurrently writes a directory map structure as a sequence of map entries distributed among the groups of user data blocks. Each map entry stores address information for the user data blocks in the associated group and a pointer to a subsequent map entry in the sequence. A control circuit accesses a first map entry in the sequence and uses the address information and pointer in the first map entry to locate the remaining map entries and the locations of the user data blocks in the respective groups. Lossless data compression may be applied to the groups prior to writing.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Inventors: Timothy Canepa, Ryan J. Goss, Stephen Hanna