Abstract: Fault tolerant and fault detecting multi-threaded processors are described. Instructions from a program are executed by both a master thread and a slave thread and execution of the master thread is prioritized. If the master thread stalls or reaches a memory write after having executed a sequence of instructions, the slave thread executes a corresponding sequence of instructions, where at least the first and last instructions in the sequence are the same as the sequence executed by the master thread. When the slave thread reaches the point at which execution of the master thread stopped, the contents of register banks for both the threads are compared, and if they are the same, execution by the master thread is allowed to continue, and any buffered speculative writes are committed to the memory system.

Abstract: Fault tolerant and fault detecting multi-threaded processors are described. Instructions from a program are executed by both a master thread and a slave thread and execution of the master thread is prioritized. If the master thread stalls or reaches a memory write after having executed a sequence of instructions, the slave thread executes a corresponding sequence of instructions, where at least the first and last instructions in the sequence are the same as the sequence executed by the master thread. When the slave thread reaches the point at which execution of the master thread stopped, the contents of register banks for both the threads are compared, and if they are the same, execution by the master thread is allowed to continue, and any buffered speculative writes are committed to the memory system.

Abstract: An integrated circuit comprising multiple master units and multiple slave units connected via interconnect circuitry utilizes token based node-to-node communication flow management within the interconnect circuitry with a network node requesting a token and receiving a token signal before it asserts its communication signals onto a physical communication link shared between multiple virtual networks.

Abstract: A data processing apparatus and method for setting priority levels for transactions has a shared resource for processing transactions, and at least one master device for issuing the transactions to the shared resource. The master device provides a plurality of sources of the transactions, and each of the transactions has a priority level associated therewith. Arbitration circuitry applies an arbitration policy to select a transaction from amongst multiple transactions issued to the shared resource. Adaptive priority circuitry is associated with at least one of the sources and monitors throughput indication data for previously issued transactions from the associated source. For each new transaction from the associated source, the circuitry sets the priority level to one of a plurality of predetermined priority levels dependent on the throughput indication data. The adaptive priority circuitry sets the lowest priority level from amongst the plurality of predetermined priority levels.

Abstract: Memory circuitry, a data processing apparatus and a method of storing data are disclosed. The memory circuitry comprises: a memory for storing the data; and control circuitry for controlling power consumption of the memory by controlling a rate of access to the memory such that an average access delay between adjacent accesses is maintained at or above a predetermined value; wherein the control circuitry is configured to determine a priority of an access request to the memory and to maintain the average access delay at or above the predetermined value by delaying at least some accesses from access requests having a lower priority for longer than at least some accesses from access requests having a higher priority.

Abstract: A memory interconnect between transaction masters and a shared memory. A first snoop request is sent to other transaction masters to trigger them to invalidate any local copy of that data they may hold and for them to return any cached line of data corresponding to the write line of data that is dirty. A first write transaction is sent to the shared memory. When and if any cached line of data is received from the further transaction masters, then the portion data is used to form a second write transaction which is sent to the shared memory and writes the remaining portions of the cached line of data which were not written by the first write transaction in to the shared memory. The serialization circuitry stalls any transaction requests to the write line of data until the first write transaction.

Abstract: A memory interconnect between transaction masters and a shared memory. A first snoop request is sent to other transaction masters to trigger them to invalidate any local copy of that data they may hold and for them to return any cached line of data corresponding to the write line of data that is dirty. A first write transaction is sent to the shared memory. When and if any cached line of data is received from the further transaction masters, then the portion data is used to form a second write transaction which is sent to the shared memory and writes the remaining portions of the cached line of data which were not written by the first write transaction in to the shared memory. The serialisation circuitry stalls any transaction requests to the write line of data until the first write transaction.

Abstract: A data processing apparatus and method for setting priority levels for transactions has a shared resource for processing transactions, and at least one master device for issuing the transactions to the shared resource. The master device provides a plurality of sources of the transactions, and each of the transactions has a priority level associated therewith. Arbitration circuitry applies an arbitration policy to select a transaction from amongst multiple transactions issued to the shared resource. Adaptive priority circuitry is associated with at least one of the sources and monitors throughput indication data for previously issued transactions from the associated source. For each new transaction from the associated source, the circuitry sets the priority level to one of a plurality of predetermined priority levels dependent on the throughput indication data. The adaptive priority circuitry sets the lowest priority level from amongst the plurality of predetermined priority levels.

Abstract: A security controller has first and second read request paths for performing security checking of read requests received from a master device and for controlling issuing of the read request to a safe device. If the first read request path is selected for an incoming read request then the first read request path controls issuing of the read request in dependence on result of the security checking. If the second read request path is selected, then the incoming read request is issued without waiting for a result of the security checking, and tracking data is stored indicating the result of the security checking. When receiving a response to a read request issued using the second read request path, a response path modifies the response to mask read data if the tracking data stored for the corresponding read request indicates that a security violation occurred.

Abstract: A data processing apparatus and method for setting priority levels for transactions is provided. The data processing apparatus has a shared resource for processing transactions, and at least one master device for issuing the transactions to the shared resource. The at least one master device provides a plurality of sources of the transactions, and each of the transactions has a priority level associated therewith. Arbitration circuitry is used to apply an arbitration policy to select a transaction from amongst multiple transactions issued to the shared resource, the arbitration policy using the priority level associated with each of the multiple transactions when performing the selection.

Abstract: An integrated circuit comprising multiple master units (4, 6) and multiple slave units (10, 12) connected via interconnect circuitry (8) utilises token based node-to-node communication flow management within the interconnect circuitry (8) with a network node requesting a token and receiving a token signal before it asserts its communication signals onto a physical communication link shared between multiple virtual networks.

Abstract: Initiator devices for generating transaction requests and recipient devices for receiving them are disclosed. The recipient devices accept transaction requests where there is available buffer storage for the transaction request. If there is no storage space available an acknowledgement signal generator generates and outputs a reject acknowledgement signal indicating a request has been received but has not been accepted by the recipient device. A credit generator can reserve at least one available storage location in the buffer and generate a credit grant for an initiator device that sent one of the transaction requests that was not accepted by the recipient device. The credit grant indicates to the initiator device that there is at least one reserved storage location, such that a subsequent transaction request from the initiator device will be accepted by the recipient device.

Abstract: Initiator devices for generating transaction requests and recipient devices for receiving them are disclosed. The recipient devices accept transaction requests where there is available buffer storage for the transaction request. If there is no storage space available an acknowledgement signal generator generates and outputs a reject acknowledgement signal indicating a request has been received but has not been accepted by the recipient device. A credit generator can reserve at least one available storage location in the buffer and generate a credit grant for an initiator device that sent one of the transaction requests that was not accepted by the recipient device. The credit grant indicates to the initiator device that there is at least one reserved storage location, such that a subsequent transaction request from the initiator device will be accepted by the recipient device.

Abstract: A security controller has first and second read request paths for performing security checking of read requests received from a master device and for controlling issuing of the read request to a safe device. If the first read request path is selected for an incoming read request then the first read request path controls issuing of the read request in dependence on result of the security checking. If the second read request path is selected, then the incoming read request is issued without waiting for a result of the security checking, and tracking data is stored indicating the result of the security checking. When receiving a response to a read request issued using the second read request path, a response path modifies the response to mask read data if the tracking data stored for the corresponding read request indicates that a security violation occurred.

Abstract: Transaction requests requesting a service from the slave device are received from a master device at a transaction interface. The transaction requests are selectively issued to the bus system under control of an issue control circuit. A target outstanding transaction value N.x is received at a control interface. The target outstanding transaction value has an integer portion N and a fractional portion x. The issue control circuit controls the transaction interface to issue the transaction requests to the bus system in dependence upon the target outstanding transaction value so that a time averaged number of outstanding transaction requests corresponds to the target outstanding transaction value.

Abstract: A data processing apparatus and method for measuring a value of a predetermined property of transactions are provided. The data processing apparatus has initiator circuitry for initiating transactions, recipient circuitry for handling each transaction initiator by the initiator circuitry, and a communication path interconnecting the initiator circuitry and the recipient circuitry via which the transactions are propagated between the initiator circuitry and the recipient circuitry. Measurement circuitry is coupled to the communication path for measuring a value of a predetermined property of the transactions, such as the latency of those transactions. The measurement circuitry has active transaction count circuitry for maintaining an indication of the number of transactions in progress, and accumulator circuitry for maintaining an accumulator value which is increased dependent on the number of transactions in progress.

Abstract: Memory circuitry, a data processing apparatus and a method of storing data are disclosed. The memory circuitry comprises: a memory for storing the data; and control circuitry for controlling power consumption of the memory by controlling a rate of access to the memory such that an average access delay between adjacent accesses is maintained at or above a predetermined value; wherein the control circuitry is configured to determine a priority of an access request to the memory and to maintain the average access delay at or above the predetermined value by delaying at least some accesses from access requests having a lower priority for longer than at least some accesses from access requests having a higher priority.

Abstract: Transaction requests requesting a service from the slave device are received from a master device at a transaction interface. The transaction requests are selectively issued to the bus system under control of an issue control circuit. A target outstanding transaction value N.x is received at a control interface. The target outstanding transaction value has an integer portion N and a fractional portion x. The issue control circuit controls the transaction interface to issue the transaction requests to the bus system in dependence upon the target outstanding transaction value so that a time averaged number of outstanding transaction requests corresponds to the target outstanding transaction value.

Abstract: A processing system 1 including a memory 10 and a cache memory 4 is provided with a page status unit 40 for providing a cache controller with a page open indication indicating one or more open pages of data values in memory. At least one of one or more cache management operations performed by the cache controller is responsive to the page open indication so that the efficiency and/or speed of the processing system can be improved.

Abstract: A data processing apparatus and method for setting priority levels for transactions is provided. The data processing apparatus has a shared resource for processing transactions, and at least one master device for issuing the transactions to the shared resource. The at least one master device provides a plurality of sources of the transactions, and each of the transactions has a priority level associated therewith. Arbitration circuitry is used to apply an arbitration policy to select a transaction from amongst multiple transactions issued to the shared resource, the arbitration policy using the priority level associated with each of the multiple transactions when performing the selection.