Abstract: One or more systems, devices, and/or methods provided herein relate to a process for in-process radio frequency (RF) signal quality analysis and amplitude adjustment of one or more RF devices. In one or more embodiments, the RF device can comprise a portion of a quantum computing system, such as of readout electronics thereof, and thus amplitude adjustment can be at a waveform generator that generates pulses to affect one or more qubits of a quantum logic circuit of the quantum computing system. Generally, an electronic device can comprise an RF tap connected to an RF signal component of a first RF signal chain, and an analysis component connected to the RF tap, the analysis component configured to convert an RF signal from the RF signal component and to compare a conversion result thereof to an expected power output that is based on historical data for a second RF signal chain.

Abstract: An apparatus includes a sampling circuit, a sense circuit, and a tuning circuit. The sampling circuit samples an input signal according to a sampling clock signal to produce a sampled signal. The sense circuit determines a scaling factor based on a distortion in the sampled signal caused by the sampling clock signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal.

Abstract: A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Abstract: A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Abstract: A transmit clock generator includes a first local clock generator and a second local clock generator, each receiving an external PLL clock signal and respectively generating first and second divided clock signals. A synchronization signal is applied to the first local clock generator and second local clock generator during a clock training period to enforce a phase relationship between the first and second divided clock signals. The synchronization signal includes at least one synchronization pulse that is applied to the first local clock generator and second local clock generator during the clock training period.

Abstract: A transmit clock generator includes a first local clock generator and a second local clock generator, each receiving an external PLL clock signal and respectively generating first and second divided clock signals. A synchronization signal is applied to the first local clock generator and second local clock generator during a clock training period to enforce a phase relationship between the first and second divided clock signals. The synchronization signal includes at least one synchronization pulse that is applied to the first local clock generator and second local clock generator during the clock training period.

Abstract: A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Abstract: A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.