Patents by Inventor Timothy D. Anderson

Timothy D. Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210124673
    Abstract: A method includes executing software code comprising a plurality of execute packets; responsive to an execute packet of the software code being executed by a data processor core, advancing a value of a test counter register; and responsive to the value of the test counter register being equal to a terminal value, triggering an event to be handled by the software code.
    Type: Application
    Filed: October 23, 2020
    Publication date: April 29, 2021
    Inventors: Kai CHIRCA, Timothy D. ANDERSON
  • Publication number: 20210124589
    Abstract: A method includes receiving an execute packet that includes a first instruction and a second instruction and executing the first instruction and the second instruction using a pipeline. Executing the first and second instructions includes storing a result of the first instruction in a holding register; determining whether an event that interrupts execution of the execute packet occurs prior to completion of the executing of the second instruction; and based on the event not occurring, committing the result of the first instruction after completion of the executing of the second instruction.
    Type: Application
    Filed: October 23, 2020
    Publication date: April 29, 2021
    Inventors: Kai CHIRCA, Timothy D. ANDERSON, Paul Daniel GAUVREAU
  • Patent number: 10990398
    Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: April 27, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy D. Anderson, Joseph Zbiciak, Kai Chirca
  • Publication number: 20210109868
    Abstract: A method includes receiving, by a memory management unit (MMU) comprising a translation lookaside buffer (TLB) and a configuration register, a request from a processor core to directly modify an entry in the TLB. The method also includes, responsive to the configuration register having a first value, operating the MMU in a software-managed mode by modifying the entry in the TLB according to the request. The method further includes, responsive to the configuration register having a second value, operating the MMU in a hardware-managed mode by denying the request.
    Type: Application
    Filed: October 12, 2020
    Publication date: April 15, 2021
    Inventors: Timothy D. ANDERSON, Joseph Raymond Michael ZBICIAK, Kai CHIRCA, Daniel Brad WU
  • Patent number: 10963252
    Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 30, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Duc Bui, Peter Richard Dent, Timothy D. Anderson
  • Patent number: 10963255
    Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 30, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Naveen Bhoria, Kai Chirca, Timothy D. Anderson, Duc Bui, Abhijeet A. Chachad, Son Hung Tran
  • Publication number: 20210011872
    Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 14, 2021
    Inventors: David M. Thompson, Timothy D. Anderson, Joseph R.M. Zbiciak, Abhijeet A. Chachad, Kai Chirca, Matthew D. Pierson
  • Publication number: 20200401406
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Inventors: Joseph Zbiciak, Timothy D. Anderson
  • Publication number: 20200401526
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 24, 2020
    Inventors: Joseph Zbiciak, Timothy D. Anderson
  • Publication number: 20200371888
    Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 26, 2020
    Inventors: Joseph Zbiciak, Timothy D. Anderson, Duc Bui, Kai Chirca
  • Publication number: 20200371788
    Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: Duc BUI, Peter Richard DENT, Timothy D. ANDERSON
  • Publication number: 20200371793
    Abstract: A method to store source data in a processor in response to a bit-reversed vector store instruction includes specifying, in respective fields of the bit-reversed vector store instruction, a first source register containing the source data and a second source register containing address data. The first source register includes a plurality of lanes and each lane contains an initial data element having an associated index value. The method also includes executing the bit-reversed vector store instruction by creating reordered source data by, for each lane, replacing the initial data element in the lane with the data element having a bit-reversed index value relative to the associated index value of the initial data element; and storing the reordered source data in contiguous locations in a memory beginning at a location specified by the address data.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: Asheesh BHARDWAJ, Dheera Balasubramanian SAMUDRALA, Timothy D. ANDERSON
  • Publication number: 20200371762
    Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 26, 2020
    Inventors: Kai CHIRCA, Timothy D. ANDERSON, Todd T. HAHN, Alan L. DAVIS
  • Publication number: 20200371784
    Abstract: A method to scale source data in a processor in response to a vector floating-point scale instruction includes specifying a first source register containing the source data, a second source register containing scale values, and a destination register to store scaled source data. The first source register includes a plurality of lanes that each contains a floating-point value and the second source register and the destination register each includes a plurality of lanes corresponding to the lanes of the first source register. The method includes executing the vector floating-point scale instruction by, for each lane in the first source register adding the scale value in the corresponding lane of the second source register to an exponent field of the floating-point value in the lane of the first source register to create a scaled floating-point value, and storing the scaled floating-point value in the corresponding lane of the destination register.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: Timothy D. ANDERSON, Duc BUI, Joseph ZBICIAK
  • Publication number: 20200371796
    Abstract: A method to reverse source data in a processor in response to a vector reverse instruction includes specifying, in respective fields of the vector reverse instruction, a source register containing the source data and a destination register. The source register includes a plurality of lanes and each lane contains a data element, and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector reverse instruction by creating reversed source data by reversing the order of the data elements, and storing the reversed source data in the destination register.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: Timothy D. ANDERSON, Duc BUI
  • Publication number: 20200371800
    Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: Kai CHIRCA, Timothy D. ANDERSON, Todd T. HAHN, Alan L. DAVIS
  • Patent number: 10795844
    Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: October 6, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: David M. Thompson, Timothy D. Anderson, Joseph R. M. Zbiciak, Abhijeet A. Chachad, Kai Chirca, Matthew D. Pierson
  • Patent number: 10768933
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: September 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joseph Zbiciak, Timothy D. Anderson
  • Patent number: 10747636
    Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joseph Zbiciak, Timothy D Anderson, Duc Bui, Kai Chirca
  • Patent number: 10732945
    Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Timothy D. Anderson, Todd T. Hahn, Alan L. Davis