Abstract: A particular method includes performing a timing analysis of a plurality of sub-units of a unit of a logic design. The method also includes identifying a set of grants, where each grant is associated with a first sub-unit having excess time based on the timing analysis. The method further includes identifying a set of requests, where each request is associated with a second sub-unit having a time deficit based on the timing analysis. The method also includes determining a position of a storage element in the logic design based on the set of grants and the set of requests. The method further includes generating an output indicating the position of the storage element.

Abstract: Method, computer program product, and system for reserving space for standard cells in a circuit layout. A matrix is formed from a pool of standard cells that connect to ports along an edge of a circuit block. The matrix is formed of columns of standard cells, wherein the columns have a length equal to or less than a length of the edge. The number of standard cells that fit in a column depends on dimensions of the standard cells in the direction of the column. The cumulative width of the matrix is equal to the number of columns sufficient to include all of the standard cells in the pool multiplied by the dimension of the standard cells in a direction orthogonal to the direction of the column. The circuit block is placed in the circuit layout such that an area defined by the matrix is reserved for the standard cells.

Abstract: A particular method includes performing a timing analysis of a plurality of sub-units of a unit of a logic design. The method also includes identifying a set of grants, where each grant is associated with a first sub-unit having excess time based on the timing analysis. The method further includes identifying a set of requests, where each request is associated with a second sub-unit having a time deficit based on the timing analysis. The method also includes determining a position of a storage element in the logic design based on the set of grants and the set of requests. The method further includes generating an output indicating the position of the storage element.

Abstract: A method and apparatus are provided for implementing enhanced physical design quality using historical placement analytics in a design of an integrated gate. Mathematical data analysis is performed to determine placement trends in order to seed an initial placement of subsequent physical design placement processes. A placement seed is generated for a subsequent placement process.

Abstract: A method and apparatus are provided for implementing enhanced physical design quality using historical placement analytics in a design of an integrated gate. Mathematical data analysis is performed to determine placement trends in order to seed an initial placement of subsequent physical design placement processes. A placement seed is generated for a subsequent placement process.

Abstract: A method and apparatus are provided for implementing enhanced physical design quality using historical placement analytics in a design of an integrated gate. Mathematical data analysis is performed to determine placement trends in order to seed an initial placement of subsequent physical design placement processes. A placement seed is generated for a subsequent placement process.

Abstract: A method and apparatus are provided for implementing enhanced physical design quality using historical placement analytics in a design of an integrated gate. Mathematical data analysis is performed to determine placement trends in order to seed an initial placement of subsequent physical design placement processes. A placement seed is generated for a subsequent placement process.

Abstract: A method, system and computer program product are provided for implementing enhanced net routing for congestion resolution of non-rectangular or rectangular hierarchical macro designs of an integrated circuit chip. Congested macro nets near a macro boundary are identified. Wiring channels are reserved outside the macro boundary, allowing congested macro nets to be routed outside the physical boundary of the macro while still being logically contained within the macro.

Abstract: A method, system and computer program product are provided for implementing enhanced net routing for congestion resolution of non-rectangular or rectangular hierarchical macro designs of an integrated circuit chip. Congested macro nets near a macro boundary are identified. Wiring channels are reserved outside the macro boundary, allowing congested macro nets to be routed outside the physical boundary of the macro while still being logically contained within the macro.

Abstract: A set of nets in an integrated circuit design, having a timing margin and traverse routing tiles, are identified. The set of nets are assigned a utilization metric based on the traversed routing tiles. A set of sparse nets are determined from the set of nets, based on the utilization metric of each net in the set of sparse nets. One or more target nets are selected from the set of sparse nets, based on the timing margin of the target nets. The target nets may be modified.

Abstract: A set of nets in an integrated circuit design, having a timing margin and traverse routing tiles, are identified. The set of nets are assigned a utilization metric based on the traversed routing tiles. A set of sparse nets are determined from the set of nets, based on the utilization metric of each net in the set of sparse nets. One or more target nets are selected from the set of sparse nets, based on the timing margin of the target nets. The target nets may be modified.

Abstract: Logic gates in a child unit of a hierarchical integrated circuit design that are visible in an abstract model of the child unit of the hierarchical integrated circuit design are marked. A hide bit is set for the marked logic gates and a modification on the child unit is performed. The marked logic gates in the child unit are preserved during modification of the child unit. The hide bit is cleared from each marked logic gate and the logic gates are unmarked when modification of the child unit is complete.

Abstract: A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.

Abstract: Logic gates in a child unit of a hierarchical integrated circuit design that are visible in an abstract model of the child unit of the hierarchical integrated circuit design are marked. A hide bit is set for the marked logic gates and a modification on the child unit is performed. The marked logic gates in the child unit are preserved during modification of the child unit. The hide bit is cleared from each marked logic gate and the logic gates are unmarked when modification of the child unit is complete.

Abstract: In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location.

Abstract: In an embodiment, a list of ports and a physical location of the ports specified in a circuit design is created. Physically adjacent port pairs are determined within the list of the ports that are physically adjacent. For each respective physically adjacent port pair, the following elements are performed: calculating a timing window overlap for a current port and a next port in the respective physically adjacent port pair, computing a timing window overlap for the current port and each following port that is within a predetermined physical distance, and if the timing window overlap between the respective physically adjacent port pair is not smaller than the timing window overlap for the current port and each following port, swapping a physical location of the adjacent port with a physical location of the following port that has a smallest timing window overlap with the current port.

Abstract: In an embodiment, a list of ports and a physical location of the ports specified in a circuit design is created. Physically adjacent port pairs are determined within the list of the ports that are physically adjacent. For each respective physically adjacent port pair, the following elements are performed: calculating a timing window overlap for a current port and a next port in the respective physically adjacent port pair, computing a timing window overlap for the current port and each following port that is within a predetermined physical distance, and if the timing window overlap between the respective physically adjacent port pair is not smaller than the timing window overlap for the current port and each following port, swapping a physical location of the adjacent port with a physical location of the following port that has a smallest timing window overlap with the current port.

Abstract: A slack-based timing budget apportionment methodology relies not only upon timing analysis-based determinations of slack in the units in an integrated circuit design, but also potential performance optimization opportunities in the logic used to implement such circuits. Logic in various units of an integrated circuit design that is amenable to being replaced with comparatively faster logic may be identified during timing budget apportionment, such that the magnitude of the slack reported for those units can be adjusted to account for such potential performance improvements. Then, when timing budgets are reapportioned using the slack calculated for each unit, additional slack is available to be reapportioned to those units needing larger timing budgets.

Abstract: A method, system and computer program product are provided for implementing enhanced net routing with improved correlation of pre-buffered and post-buffered routes on a hierarchical design of an integrated circuit chip. In initial wiring steps the nets are routed, and then buffers are add along the net route based upon predetermined electrical parameters. Responsive to adding the buffers, distance based constraints are added to the nets. Then the nets that have been modified are rerouted.

Abstract: A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.