Abstract: A method and architecture for mitigating configuration memory imprinting in programmable logic devices. At power-up, a configuration memory inversion control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal time in each mode over the system's lifecycle. A configuration memory (CM) input inversion plane is positioned between a CM controller and the CM cells, and a CM output inversion plane is positioned between the CM cells and the FPGA function blocks. When running in inversion mode, data to/from the CM cells is inverted (0's and 1's are swapped) by the input and output inversion planes. By balancing time individual memory addresses spend in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as a processor's external RAM and internal cache, is also disclosed.

Abstract: A method and architecture for mitigating memory imprinting in electronic system volatile memory. At system power-up, a bus mode register control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal amounts of time in each mode over the system's lifecycle. A bi-directional data bus inverter is positioned between a system processor and volatile memory. When the system is running in inversion mode, data from non-volatile memory is inverted (0's and 1's are swapped) when copied to volatile memory, and the data bus inverter rectifies all data bits flowing in/out of the processor. By balancing the time spent by individual memory addresses in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as internal processor cache memory, and FPGA configuration memory, is also disclosed.

Abstract: A method and architecture for mitigating memory imprinting in electronic system volatile memory. At system power-up, a bus mode register control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal amounts of time in each mode over the system's lifecycle. A bi-directional data bus inverter is positioned between a system processor and volatile memory. When the system is running in inversion mode, data from non-volatile memory is inverted (0's and 1's are swapped) when copied to volatile memory, and the data bus inverter rectifies all data bits flowing in/out of the processor. By balancing the time spent by individual memory addresses in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as internal processor cache memory, and FPGA configuration memory, is also disclosed.

Abstract: A method and architecture for mitigating configuration memory imprinting in programmable logic devices. At power-up, a configuration memory inversion control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal time in each mode over the system's lifecycle. A configuration memory (CM) input inversion plane is positioned between a CM controller and the CM cells, and a CM output inversion plane is positioned between the CM cells and the FPGA function blocks. When running in inversion mode, data to/from the CM cells is inverted (0's and 1's are swapped) by the input and output inversion planes. By balancing time individual memory addresses spend in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as a processor's external RAM and internal cache, is also disclosed.