Patents by Inventor Timothy D. Wig

Timothy D. Wig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10999924
    Abstract: An apparatus comprising includes a first pair of conductors to carry differential signals, at least one ground conductor neighboring the first pair of conductors, the ground conductor to be connected to a ground plane, and at least one particular conductor to carry sideband signals. The particular conductor is to be connected to a ground plane via a resonance mitigation circuit, and the resonance mitigation circuit comprises a resistor.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Timothy D. Wig, Steven K. Krooswyk, Marc Wells
  • Patent number: 10996825
    Abstract: Systems, apparatuses and methods may provide for an electronic spine and one or more digital pages removably attached to the electronic spine, wherein the one or more digital pages include a first side with a first flexible display and a second side with a second flexible display. In one example, the system may further include a magnetic interface, wherein the digital page is removably attached to the electronic spine via the magnetic interface.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Christian Karl, Charles Magnuson, Sergei Babokhov, Timothy D. Wig
  • Patent number: 10811823
    Abstract: A system board is provided that includes a connector. The connector includes a pinfield. The pinfield includes a set of differential signal conductors to correspond to pins of a set of differential signaling pairs; a set of one or more auxiliary signal conductors to carry auxiliary signals; and a plurality of thru-hole ground vias adjacent to a particular one of the auxiliary signal conductors in the set of auxiliary signal conductors. A method for improving signal integrity in a computer interconnect can include carrying differential signals on a set of differential signal vias in a connector pinfield; carrying sideband signals on a set of sideband vias in the connector pinfield; and reducing via-to-via crosstalk between a particular one of the sideband vias and one of the differential signal vias through one or more thru-hole ground vias adjacent to the particular sideband via in the pinfield.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventor: Timothy D. Wig
  • Publication number: 20200275549
    Abstract: An apparatus comprising includes a first pair of conductors to carry differential signals, at least one ground conductor neighboring the first pair of conductors, the ground conductor to be connected to a ground plane, and at least one particular conductor to carry sideband signals. The particular conductor is to be connected to a ground plane via a resonance mitigation circuit, and the resonance mitigation circuit comprises a resistor.
    Type: Application
    Filed: December 20, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Timothy D. Wig, Steven K. Krooswyk, Marc Wells
  • Patent number: 10602607
    Abstract: An apparatus comprising includes a first pair of conductors to carry differential signals, at least one ground conductor neighboring the first pair of conductors, the ground conductor to be connected to a ground plane, and at least one particular conductor to carry sideband signals. The particular conductor is to be connected to a ground plane via a resonance mitigation circuit, and the resonance mitigation circuit comprises a resistor.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Timothy D. Wig, Steven K. Krooswyk, Marc Wells
  • Patent number: 10517168
    Abstract: An apparatus comprising includes a first pair of conductors to carry differential signals, at least one ground conductor neighboring the first pair of conductors, the ground conductor to be connected to a ground plane, and at least one particular conductor to carry sideband signals. The particular conductor is to be connected to a ground plane via a resonance mitigation circuit, and the resonance mitigation circuit comprises a resistor.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Timothy D. Wig, Steven K. Krooswyk, Marc Wells
  • Publication number: 20190021165
    Abstract: An apparatus comprising includes a first pair of conductors to carry differential signals, at least one ground conductor neighboring the first pair of conductors, the ground conductor to be connected to a ground plane, and at least one particular conductor to carry sideband signals. The particular conductor is to be connected to a ground plane via a resonance mitigation circuit, and the resonance mitigation circuit comprises a resistor.
    Type: Application
    Filed: May 14, 2018
    Publication date: January 17, 2019
    Applicant: Intel Corporation
    Inventors: Timothy D. Wig, Steven K. Krooswyk, Marc Wells
  • Publication number: 20180331472
    Abstract: A system board is provided that includes a connector. The connector includes a pinfield. The pinfield includes a set of differential signal conductors to correspond to pins of a set of differential signaling pairs; a set of one or more auxiliary signal conductors to carry auxiliary signals; and a plurality of thru-hole ground vias adjacent to a particular one of the auxiliary signal conductors in the set of auxiliary signal conductors.
    Type: Application
    Filed: July 23, 2018
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventor: Timothy D. Wig
  • Patent number: 10038281
    Abstract: A circuit board is provided including a top ground plane, a bottom ground plane, and a pin field of a connector with a plurality of pins that includes a plurality of differential pin pairs, one or more ground pins, and one or more sideband pins. At least a particular one of the sideband pins is positioned within the pin field adjacent to a first pin of a first one of the differential pin pairs. One or more ground vias are provided on the circuit board positioned to correspond to the particular sideband pin.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 31, 2018
    Assignee: Intel Corporation
    Inventor: Timothy D. Wig
  • Patent number: 9974161
    Abstract: An apparatus comprising includes a first pair of conductors to carry differential signals, at least one ground conductor neighboring the first pair of conductors, the ground conductor to be connected to a ground plane, and at least one particular conductor to carry sideband signals. The particular conductor is to be connected to a ground plane via a resonance mitigation circuit, and the resonance mitigation circuit comprises a resistor.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Timothy D. Wig, Steven K. Krooswyk, Marc Wells
  • Publication number: 20170364220
    Abstract: Systems, apparatuses and methods may provide for an electronic spine and one or more digital pages removably attached to the electronic spine, wherein the one or more digital pages include a first side with a first flexible display and a second side with a second flexible display. In one example, the system may further include a magnetic interface, wherein the digital page is removably attached to the electronic spine via the magnetic interface.
    Type: Application
    Filed: June 20, 2016
    Publication date: December 21, 2017
    Applicant: Intel Corporation
    Inventors: Christian Karl, Charles Magnuson, Sergei Babokhov, Timothy D. Wig
  • Patent number: 9599661
    Abstract: Embodiments of the invention describe apparatuses, systems and method for utilizing testing instruments having electrical interconnects formed from High Density Interconnect (HDI) multi-layer substrates. Electrical signals may be routed between devices mounted on HDI substrates by way of conductive interconnects formed within their multiple layers. The conductive interconnects are generally comprised of metal interconnects and vias, where each via penetrates between layers to couple a metal interconnect from one layer to a metal interconnect from another layer. By utilizing HDI substrates, embodiments of the invention enable “breaking out” the signal pins on multiple layers, perhaps double or triple the routing layers of the package channel; however, the geometry of the transmission lines and other factors may be chosen to ensure channel parameters such as impedance and crosstalk closely emulate the final device package.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventor: Timothy D. Wig
  • Publication number: 20170047686
    Abstract: A circuit board is provided including a top ground plane, a bottom ground plane, and a pin field of a connector with a plurality of pins that includes a plurality of differential pin pairs, one or more ground pins, and one or more sideband pins. At least a particular one of the sideband pins is positioned within the pin field adjacent to a first pin of a first one of the differential pin pairs. One or more ground vias are provided on the circuit board positioned to correspond to the particular sideband pin.
    Type: Application
    Filed: September 25, 2015
    Publication date: February 16, 2017
    Inventor: Timothy D. Wig
  • Patent number: 9560760
    Abstract: Techniques for reducing resonance in contact fingers of a connector are described herein. An example of a device in accordance with the present techniques includes an add-in-card that includes a circuit board and an edge contact finger disposed on an outer surface of the circuit board. The add-in-card also includes a resonator disposed in an internal layer of the circuit board and coupled to the edge contact finger, wherein the resonator reduces a resonance in the edge contact finger.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: January 31, 2017
    Assignee: Intel Corporation
    Inventor: Timothy D. Wig
  • Publication number: 20160380393
    Abstract: An apparatus comprising includes a first pair of conductors to carry differential signals, at least one ground conductor neighboring the first pair of conductors, the ground conductor to be connected to a ground plane, and at least one particular conductor to carry sideband signals. The particular conductor is to be connected to a ground plane via a resonance mitigation circuit, and the resonance mitigation circuit comprises a resistor.
    Type: Application
    Filed: March 24, 2016
    Publication date: December 29, 2016
    Inventors: Timothy D. Wig, Steven K. Krooswyk, Marc Wells
  • Publication number: 20140357105
    Abstract: Techniques for reducing resonance in contact fingers of a connector are described herein. An example of a device in accordance with the present techniques includes an add-in-card that includes a circuit board and an edge contact finger disposed on an outer surface of the circuit board. The add-in-card also includes a resonator disposed in an internal layer of the circuit board and coupled to the edge contact finger, wherein the resonator reduces a resonance in the edge contact finger.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Inventor: Timothy D. Wig
  • Publication number: 20140084954
    Abstract: Embodiments of the invention describe apparatuses, systems and method for utilizing testing instruments having electrical interconnects formed from High Density Interconnect (HDI) multi-layer substrates. Electrical signals may be routed between devices mounted on HDI substrates by way of conductive interconnects formed within their multiple layers. The conductive interconnects are generally comprised of metal interconnects and vias, where each via penetrates between layers to couple a metal interconnect from one layer to a metal interconnect from another layer. By utilizing HDI substrates, embodiments of the invention enable “breaking out” the signal pins on multiple layers, perhaps double or triple the routing layers of the package channel; however, the geometry of the transmission lines and other factors may be chosen to ensure channel parameters such as impedance and crosstalk closely emulate the final device package.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventor: Timothy D. Wig
  • Patent number: 7342969
    Abstract: At least two sequences of predetermined reference times are established on respective ones of at least two communication lines. At least some of the reference times of at least one of the sequences occur out-of-phase with at least some of the reference times of another of the sequences. Digital data is encoded onto data signals on one or more communication lines such that a time difference between at least one of the data signals and the nearest one of the reference times on one of the communication lines is smaller than the time difference between the same data signal and the nearest one of the reference times on another one of the communication lines.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: March 11, 2008
    Assignee: Intel Corporation
    Inventors: Larry R. Tate, Timothy D. Wig