Patents by Inventor Timothy Dalton
Timothy Dalton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7497959Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.Type: GrantFiled: May 11, 2004Date of Patent: March 3, 2009Assignee: International Business Machines CorporationInventors: Deok-kee Kim, Kenneth T. Settlemyer, Jr., Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens, Dirk Pfeiffer, Timothy Dalton, Katherina Babich, Arpan P. Mahorowala, Harald Okorn-Schmidt
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Patent number: 7462509Abstract: An method of packaging an electronic device. The method for packaging the device including: providing a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.Type: GrantFiled: May 16, 2006Date of Patent: December 9, 2008Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Mark David Jaffe, Christopher David Muzzy, Wolfgang Sauter, Edmund Sprogis, Anthony Kendall Stamper
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Publication number: 20080254643Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: ApplicationFiled: June 23, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Darren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang
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Patent number: 7402532Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: GrantFiled: August 4, 2006Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Derren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang
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Publication number: 20080092367Abstract: A method of fabricating a MEMS switch having a free moving inductive element within in micro-cavity guided by at least one inductive coil. The switch consists of an upper inductive coil at one end of a micro-cavity; optionally, a lower inductive coil; and a free-moving inductive element preferably made of magnetic material. The coils are provided with an inner permalloy core. Switching is achieved by passing a current through the upper coil, inducing a magnetic field unto the inductive element. The magnetic field attracts the free-moving inductive element upwards, shorting two open conductive wires, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the conductive wires open. When the chip is not mounted with the correct orientation, the lower coil pulls the free-moving inductive element back at its original position.Type: ApplicationFiled: January 3, 2008Publication date: April 24, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis Hsu, Lawrence Clevenger, Timothy Dalton, Carl Radens, Keith Wong, Chih-Chao Yang
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Publication number: 20080093342Abstract: Method of operating an apparatus which allows etching different substrate etch areas of a substrate having different pattern densities at essentially the same etch rate. The apparatus includes (a) a chamber; (b) an anode and a cathode in the chamber; and (c) a bias power system coupled to the cathode, wherein the cathode includes multiple cathode segments. The operation method is as follows. A substrate to be etched is placed between the anode and cathode, wherein the substrate includes N substrate etch areas, and the N substrate etch areas are directly above the N cathode segments. N bias powers are determined which when being applied to the N cathode segments during an etching of the substrate, will result in essentially a same etch rate for the N substrate etch areas. Then, the bias power system is used to apply the N bias powers the N cathode segments.Type: ApplicationFiled: December 21, 2007Publication date: April 24, 2008Inventors: Timothy Dalton, Emily Gallagher, Louis Kindt, Carey Thiel, Andrew Watts
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Publication number: 20080083697Abstract: A novel asymmetric filter membrane, and process for making is disclosed in several exemplary versions. The membrane structure is physically robust and suitable for use in a wide variety of applications. The support membrane is may be comprised of material such as a porous silicon or a silicon oxide, and the separation membrane may be comprised of material such as a polymer, zeolite film, or silicon oxide. The process relies on steps adapted from the microelectronics industry.Type: ApplicationFiled: October 15, 2007Publication date: April 10, 2008Inventors: Timothy Dalton, Michelle Steen
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Patent number: 7348870Abstract: A hinge type MEMS switch that is fully integratable within a semiconductor fabrication process, such as a CMOS, is described. The MEMS switch constructed on a substrate consists of two posts, each end thereof terminating in a cap; a movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; an upper and lower electrode pairs; and upper and lower interconnect wiring lines connected and disconnected by the movable conductive plate. When in the energized state, a low voltage level is applied to the upper electrode pair, while the lower electrode pair is grounded. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines.Type: GrantFiled: January 5, 2005Date of Patent: March 25, 2008Assignee: International Business Machines CorporationInventors: Louis C. Hsu, Timothy Dalton, Lawrence Clevenger, Carl Radens, Kwong Hon Wong, Chih-Chao Yang
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Publication number: 20080054393Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.Type: ApplicationFiled: October 30, 2007Publication date: March 6, 2008Inventors: Anil Chinthakindi, Timothy Dalton, Ebenezer Eshun, Jeffrey Gambino, Anthony Stamper, Kunal Vaed
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Publication number: 20080047118Abstract: A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalls of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalls of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalls of the aperture is vertical and separated by a second pair of opposite sidewalls that is outward sloped.Type: ApplicationFiled: October 26, 2007Publication date: February 28, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Dalton, Jeffrey Gambino, Anthony Stamper
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Publication number: 20080038917Abstract: Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.Type: ApplicationFiled: October 17, 2007Publication date: February 14, 2008Applicant: International Business Machines CorporationInventors: Timothy Dalton, Nicholas Fuller, Stephen Gates
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Publication number: 20080038915Abstract: Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.Type: ApplicationFiled: August 31, 2007Publication date: February 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel EDELSTEIN, Matthew COLBURN, Edward COONEY, Timothy DALTON, John FITZSIMMONS, Jeffrey GAMBINO, Elbert HUANG, Michael LANE, Vincent MCGAHAY, Lee NICHOLSON, Satyanarayana NITTA, Sampath PURUSHOTHAMAN, Sujatha SANKARAN, Thomas SHAW, Andrew SIMON, Anthony STAMPER
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Publication number: 20080038923Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.Type: ApplicationFiled: September 6, 2007Publication date: February 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel EDELSTEIN, Matthew COLBURN, Edward COONEY, Timothy DALTON, John FITZSIMMONS, Jeffrey GAMBINO, Elbert HUANG, Michael LANE, Vincent MCGAHAY, Lee NICHOLSON, Satyanarayana NITTA, Sampath PURUSHOTHAMAN, Sujatha SANKARAN, Thomas SHAW, Andrew SIMON, Anthony STAMPER
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Publication number: 20080014744Abstract: A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.Type: ApplicationFiled: September 25, 2007Publication date: January 17, 2008Inventors: Chih-Chao Yang, Lawrence Clevenger, Andrew Cowley, Timothy Dalton, Meeyoung Yoon
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Publication number: 20080014663Abstract: A hinge type MEMS switch that is fully integratable within a semiconductor fabrication process such as a CMOS, is described. The MEMS switch constructed on a substrate consists of two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; upper and lower electrode pairs; and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. When in the energized state, a low voltage level is applied to the upper electrode pair, while the lower electrode pair is grounded. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines.Type: ApplicationFiled: July 12, 2007Publication date: January 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis Hsu, Timothy Dalton, Lawrence Clevenger, Carl Radens, Kwong Wong, Chih-Chao Yang
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Publication number: 20080006944Abstract: A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.Type: ApplicationFiled: September 25, 2007Publication date: January 10, 2008Inventors: Chih-Chao Yang, Lawrence Clevenger, Andrew Cowley, Timothy Dalton, Meeyoung Yoon
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Publication number: 20070281469Abstract: The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.Type: ApplicationFiled: August 15, 2007Publication date: December 6, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence Clevenger, Timothy Dalton, Louis Hsu, Conal Murray, Carl Radens, Kwong-Hon Wong, Chih-Chao Yang
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Publication number: 20070267746Abstract: An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.Type: ApplicationFiled: May 16, 2006Publication date: November 22, 2007Inventors: Kerry Bernstein, Timothy Dalton, Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Mark David Jaffe, Christopher David Muzzy, Wolfgang Sauter, Edmund Sprogis, Anthony Kendall Stamper
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Publication number: 20070267698Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.Type: ApplicationFiled: July 9, 2007Publication date: November 22, 2007Inventors: Kerry Bernstein, Timothy Dalton, Jeffrey Gambino, Mark Jaffe, Paul Kartschoke, Anthony Stamper
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Publication number: 20070266129Abstract: Disclosed herein is a multi-layer silicon stack architecture including: one or more processing layers including one or more computing elements; one or more networking layers disposed between the processing layers, the network layer includes one or more networking elements, wherein each computing element includes a plurality of network connections to adjacently disposed networking elements.Type: ApplicationFiled: May 12, 2006Publication date: November 15, 2007Applicant: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Marc Faucher, Peter Sandon