Abstract: A data transmission scheduler subsystem for a multi-channel bank communication system architecture contains a plurality of ‘per port’ schedulers. Each per port scheduler is resident in the system's primary channel bank, and is operative to controllably cause customer-destined data, that has been buffered from a communication network into switch fabric storage circuitry of the primary channel bank, to be controllably read out for downlink transmission to associated destination data ports of the channel banks at the destination data ports' data rates.

Abstract: A policing engine for use in a telecommunication equipment shelf is operative to control the rate at which customer-sourced ATM packets are passed to buffers associated with different classes of service to which customers may subscribe. The policing engine examines the rate at which ATM cells are supplied to it from the line card ports, whether the cells are AAL5 cells, and how full are the buffers into which the cells are to be written. If cells are supplied to the policing engine at a rate faster than prescribed peak or sustained cell rates, or if the cell buffer begins to fill up, the policing engine controllably discards incoming cells, thereby effectively ‘throttling’ the cell flow rate through it.

Abstract: A single switch fabric-based, multi-channel bank digital subscriber line access multiplexer includes a master channel bank containing a master switch module in which the switch fabric and a downstream-directed traffic scheduler reside, and one or more expansion channel banks that are linked with the master channel bank by way of upstream and downstream communication links. Distributed among the channel banks are respective policing mechanisms and cell rate control mechanisms that control upstream-directed communications from line card ports of each expansion channel bank to the switch fabric. Downstream data transmissions are locked to network timing, and are scheduled by a centralized scheduling mechanism resident in the master channel bank.

Abstract: An inter-channel bank addressing and identification protocol, for use with a multi channel bank, digital subscriber line access multiplexer (DSLAM), enables the control processor of a master channel bank to selectively communicate with control processors of subtended slave channel banks, and allows a subtended slave shelf to retain provisioning information, irrespective of a change in shelf location or removal of a subtended slave shelf between the master shelf and another subtended slave shelf. The inter-channel bank addressing and identification protocol uses a shelf address code that is controllably incremented or decremented during the transport of a packet between the master and a slave shelf. In addition, a shelf address code is assigned each slave shelf during initialization. These two codes enable the master to track which channel bank is in which shelf bay.