Abstract: A reconfigurable neural circuit includes an array of processing nodes. Each processing node includes a single physical neuron circuit having only one input and an output, a single physical synapse circuit having a presynaptic input, and a single physical output coupled to the input of the neuron circuit, a weight memory for storing N synaptic conductance value or weights having an output coupled to the single physical synapse circuit, a single physical spike timing dependent plasticity (STDP) circuit having an output coupled to the weight memory, a first input coupled to the output of the neuron circuit, and a second input coupled to the presynaptic input, and interconnect circuitry connected to the presynaptic input and connected to the output of the single physical neuron circuit. The synapse circuit and the STDP circuit are each time multiplexed circuits. The interconnect circuitry in each respective processing node is coupled to the interconnect circuitry in each other processing node.

Abstract: A reconfigurable neural circuit includes an array of processing nodes. Each processing node includes a single physical neuron circuit having only one input and an output, a single physical synapse circuit having a presynaptic input, and a single physical output coupled to the input of the neuron circuit, a weight memory for storing N synaptic conductance value or weights having an output coupled to the single physical synapse circuit, a single physical spike timing dependent plasticity (STDP) circuit having an output coupled to the weight memory, a first input coupled to the output of the neuron circuit, and a second input coupled to the presynaptic input, and interconnect circuitry connected to the presynaptic input and connected to the output of the single physical neuron circuit. The synapse circuit and the STDP circuit are each time multiplexed circuits. The interconnect circuitry in each respective processing node is coupled to the interconnect circuitry in each other processing node.

Abstract: A reconfigurable neural circuit includes an array of processing nodes. Each processing node includes a single physical neuron circuit having only one input and an output, a single physical synapse circuit having a presynaptic input, and a single physical output coupled to the input of the neuron circuit, a weight memory for storing N synaptic conductance value or weights having an output coupled to the single physical synapse circuit, a single physical spike timing dependent plasticity (STDP) circuit having an output coupled to the weight memory, a first input coupled to the output of the neuron circuit, and a second input coupled to the presynaptic input, and interconnect circuitry connected to the presynaptic input and connected to the output of the single physical neuron circuit. The synapse circuit and the STDP circuit are each time multiplexed circuits. The interconnect circuitry in each respective processing node is coupled to the interconnect circuitry in each other processing node.

Abstract: A circuit for emulating the behavior of biological neural circuits, the circuit including a plurality of nodes wherein each node comprises a neuron circuit, a time multiplexed synapse circuit coupled to an input of the neuron circuit, a time multiplexed short term plasticity (STP) circuit coupled to an input of the node and to the synapse circuit, a time multiplexed Spike Timing Dependent Plasticity (STDP) circuit coupled to the input of the node and to the synapse circuit, an output of the node coupled to the neuron circuit; and an interconnect fabric coupled between the plurality of nodes for providing coupling from the output of any node of the plurality of nodes to any input of any other node of the plurality of nodes.

Abstract: A circuit for emulating the behavior of biological neural circuits, the circuit including a plurality of nodes wherein each node comprises a neuron circuit, a time multiplexed synapse circuit coupled to an input of the neuron circuit, a time multiplexed short term plasticity (STP) circuit coupled to an input of the node and to the synapse circuit, a time multiplexed Spike Timing Dependent Plasticity (STDP) circuit coupled to the input of the node and to the synapse circuit, an output of the node coupled to the neuron circuit; and an interconnect fabric coupled between the plurality of nodes for providing coupling from the output of any node of the plurality of nodes to any input of any other node of the plurality of nodes.

Abstract: A reconfigurable neural circuit includes a two dimensional array including a plurality of processing nodes, wherein each processing node includes a neuron circuit, a synapse circuit, a spike timing dependent plasticity (STDP) circuit, a weight memory for storing synaptic weights, the weight memory coupled to the synapse circuit, an interconnect fabric for interconnections to and from and between the neuron circuit, the synapse circuit, the STDP circuit, the weight memory, and between a respective node in the array and other processing nodes in the array, and a connectivity memory for storing interconnect routing controls coupled to the interconnect fabric.

Abstract: A monolithic frequency converter using a feedback control loop generates a source of synthesized frequency signals over a wide dynamic range based on a timing source such as a crystal oscillator or an external frequency source. The frequency converter includes a controlled oscillator, a frequency counter, a timing signal generator and, connected between the frequency counter and the controlled oscillator, a digital to analog converter and a difference integrator. The controlled oscillator generates a clock signal at a frequency controlled by an electrical signal. The difference integrator is connected to an input signal terminal and connected to the timing signal generator. The difference integrator determines a difference signal between the input signal and a signal operated upon by the digital to analog converter and integrates the difference signal under control of a timing signal generated by the timing signal generator.