Abstract: A system for streaming a plurality of video or other recorded signals from storage to receiving devices maintains each of the signal streams at their encoded bit rate. The bit rate of each stream is detected from the stored signals and a corresponding queue is set up in memory or in a network interface card for outputting data at the detected bit rate. A channel timing module in the signal streaming device contains a two-stage dithered counter for each bit rate. The first stage of the counter counts one clock cycle longer than the second stage. By adjusting the ratio of the first stage and second stage counters in a fixed number of cycles (the dither cycle) a very precise average count is achieved. The average count is calculated to achieve the desired bit rate with a given packet size. Every time either the first stage of the second counter times out, a packet of data is sent to the corresponding queue in the network interface.