Abstract: A method for fabricating interlevel contacts in semiconductor integrated circuits provides for formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

Abstract: Interlevel contacts in semiconductor integrated circuits are fabricated by formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

Abstract: A memory for a dynamic random access memory includes an isolation trench formed between a pair of cells. Pass gate transistors are formed on either side of the isolation trench, with source/drain regions for contacting to a bit line formed on the opposite side of a gate electrode from the isolation trench. A source/drain region for each transistor is formed between the gate electrode and the isolation trench, and is used for a charge storage capacitor connection. For each transistor, a conductive plug is formed in contact with the capacitor source/drain region and extending vertically above this region and the gate electrode. This conductive plug forms the charge storage node of the capacitor, and is covered by a dielectric layer and a common capacitor reference plate.

Abstract: A method for forming a memory cell for a dynamic random access memory includes the steps of first forming the transistors having gate electrodes (34) and source/drain regions (44) on either side thereof. An isolation trench (48) is formed in one of the source/drain regions with a portion (52) remaining. A masking layer (56) is formed over the surface of the substrate and an opening (62) formed therein to expose the source/drain region (52) and associated tungsten layer (50). A conductive plug (62) is formed in the opening followed by formation of an oxide layer (66). The plug (62) comprises the lower plate of the capacitor and then a conformal layer of conductive material (68) is formed over the surface thereof to comprise the upper plate of the capacitor. A planarized layer of oxide (69) is formed over the substrate and an opening (70) formed therein to expose the other of the source/drain regions (44). A contact plug (76) is formed in the opening (70) followed by formation of the interconnect layer (78).

Abstract: A method for improving the corrosion resistance of aluminum in a semiconductor device. The step includes providing a semiconductor device having aluminus containing contact pads; attaching a leadframe to the contact pads; and applying sufficient zinc chromate in solution to the contact pads for a sufficient time and at a sufficient temperature to render said aluminum substantially resistant to corrosion.

Abstract: Testing of the gate oxides of all the transistors of a single die in a silicon wafer to be diced into a plurality of dice in a single operation is effected at an intermediate stage of the fabrication process by providing a metal layer contacting selectively each of the gate electrodes of a die at an intermediate stage of the processing and providing between the layer and the wafer a voltage of amplitude insufficient to cause significant tunneling current through good gate oxides but sufficient to cause significant tunneling current through defective gate oxides.

Abstract: A method for improving the corrosion resistance of aluminum in a semiconductor device. The step includes providing a semiconductor device having aluminum containing contact pads; attaching a leadframe to the contact pads; and applying sufficient zinc chromate in solution to the contact pads for a sufficient time and at a sufficient temperature to render said aluminum substantially resistant to corrosion.

Abstract: Testing of the gate oxides of all the transistors of a single die in a silicon wafer to be diced into a plurality of dice in a single operation is effected at an intermediate stage of the fabrication process by providing a metal layer contacting selectively each of the gate electrodes of a die at an intermediate stage of the processing and providing between the layer and the wafer a voltage of amplitude insufficient to cause significant tunneling current through good gate oxides but sufficient to cause significant tunneling current through defective gate oxides.