Abstract: A compound semiconductor device is comprising a compound semiconductor substrate (219) having a ground plane (205); an active element (201) disposed on the substrate; a passive element (211) disposed on the substrate and electrically coupled to the active element; and an insulating layer (202) adjacent the substrate and interposed between the passive device and ground surface such that there is no resistive ground path from the passive device to the ground surface.

Abstract: A heterojunction P-I-N diode switch comprises a first layer of doped semiconductor material of a first doping type, a second layer of doped semiconductor material of a second doping type and a substrate on which is disposed the first and second layers. An intrinsic layer of semiconductor material is disposed between the first layer and second layer. The semiconductor material composition of at least one of the first layer and second layer is sufficiently different from that of the intrinsic layer so as to form a heterojunction therebetween, creating an energy barrier in which injected carriers from the junction are confined by the barrier, effectively reducing the series resistance within the I region of the P-I-N diode and the insertion loss relative to that of homojunction P-I-N diodes.

Abstract: An electric component package having a base and a lid, the base and lid defining a hermetically sealed cavity therebetween for accommodating an electric component. The base includes at least one conductive via extending therethrough, allowing control and/or input/output (I/O) ports associated with the electric component to be coupled to the conducive vias to pass signals between the sealed cavity and the exterior of the package without passing through the junction between the base and lid. The electric component package can be produced at the wafer level using conventional silicon wafer integrated circuit manufacturing machinery prior to separating the wafer into a plurality of devices.

Abstract: A method of fabricating a hyperabrupt junction varactor diode structure comprises the steps of forming a non-uniformly doped n-type, hyperabrupt cathode region in a layer of semiconductor material and depositing, by ultra high vacuum chemical vapor deposition (UHVCVD), a p-type anode region onto a surface of the hyperabrupt cathode region. The deposition process is performed at relatively low temperature (i.e., below 600° C.). The anode region and the hyperabrupt cathode are joined at a junction between them such that an impurity concentration level of the hyperabrupt region increases in a direction toward the junction. During the forming step, n-type impurity ions are implanted at an implantation energy level substantially less than 300 keV, preferably between from about 10 to about 70 keV, with the implanted ions being thermally activated at a relatively low temperature (between from about 700 to about 800° C.).

Abstract: A process for fabricating heterolithic microwave integrated circuits. According to one exemplary embodiment, a glass substrate is fused to a silicon wafer, and the silicon wafer is etched to effect silicon pedestals. A glass layer is fused onto and about the silicon mesas and effectively polished to expose the tops of the silicon mesas. The backside glass layer is then polished to render a final thickness of the dielectric layer between the top surface and ground plane. In another exemplary embodiment, a layer of silicon may be selectively etched to form mesas that function as either pedestals or vias. A layer of glass may be fused to the silicon prior to etching. A layer of glass is fused to the silicon substrate and pedestals and planarized through standard polishing techniques. The wafer may be "flipped over" and polished in order to remove a substantial portion of the silicon or glass, depending on which is used. Thereafter, the integrated circuit is fabricated through standard techniques.

Abstract: A ballasted transistor structure reduces thermal runaway. A heterojunction bipolar junction transistor array includes a plurality of transistors, each having an emitter, a base and a collector. Each of the bases is an alloy of silicon and germanium and each of the collectors and emitters is silicon. A ballast resistor, of doped silicon, that prevents thermal runaway, is electrically connected to each of the collectors.

Abstract: Silicon conductive vias and pedestals are disclosed for use in microwave integrated circuits. The pedestals are isolated from a ground plane on the bottom surface by glass, while the vias are used to make electrical contact to ground. Electrical circuit elements in the top surface of the integrated circuit are selectively grounded or isolated by the choice of connection to a via or pedestal, respectively.

Abstract: A method that enables the fabrication of ballast resistors in polysilicon which can be fabricated in a manner so as to not relax the strained layers in the lattice of the silicon germanium transistor wherein the high temperature steps, associated with activating dopants to fabricate resistors with desired resistance values, are performed prior to the deposited epitaxial layers of silicon germanium.

Abstract: A method of fabricating a bipolar junction transistor having emitter line spacings on the order of approximately 0.25 microns or less is disclosed. Windows are opened in the silicon dioxide layer for the emitter collector and base fabrication. A layer of silicon nitride is disposed on top of the layer of silicon dioxide having been deposited over he entire surface containing approximately 0.5 width line features at he emitter, base and collector sites. Silicon nitride is deposited by low pressure chemical vapor deposition (LPCVD). The deposited nitride film is etched using a standard reactive ion etching technique, removing the silicon nitride from the horizontal surfaces of the oxide without removing the nitride from the sidewalls of the etched opening at the emitter, base and collector sites. The result of the RIE etching is that the thickness of the film on the horizontal surfaces is removed without removal of the nitride from the sidewalls of the etched pattern.