Patents by Inventor Timothy Edwards

Timothy Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220043956
    Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Publication number: 20220027544
    Abstract: Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.
    Type: Application
    Filed: October 4, 2021
    Publication date: January 27, 2022
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Patent number: 11231351
    Abstract: A portable flexure fixture including a fixture housing, a translatable plug, a load ring, and a support ring. The fixture housing includes a first end opposite a second end, a plug receiving opening extending into the first end and a test opening extending into the second end. The support ring is disposed in the fixture housing. The translatable plug is insertable into the plug receiving opening of the fixture housing and is translatable in both a sample engaging direction and a sample releasing direction. Further, the load ring is coupled to the translatable plug and is positioned at a sample facing end of the translatable plug such that translation of the translatable plug in the sample engaging direction translates the load ring in the sample engaging direction and translation of the translatable plug in the sample releasing direction translates the load ring in the sample releasing direction.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: January 25, 2022
    Assignee: Corning Incorporated
    Inventor: Timothy Edward Meyer
  • Publication number: 20220007896
    Abstract: Disclosed herein are a mobile dispensing device and station for dispensing a sanitizing agent. In one aspect, a mobile dispending station can include a container base configured to releasably secure a container, the container base comprising a base housing and a securing mechanism for releasably securing the container in the housing; and a dispenser column comprising: a dispenser system including a dispenser head and switch or pedal, the dispenser system in fluid communication with the container and configured to selectively dispense a predetermined volume of the sanitizing agent from within the container and through the dispenser head, the switch or pedal configured to selectively dispense the sanitizing agent upon activation or actuation, and a column housing for containing the dispenser system. Also disclosed herein are methods of using the disclosed devices and stations.
    Type: Application
    Filed: July 8, 2021
    Publication date: January 13, 2022
    Inventors: Michael Maloney, Timothy Edward Zollers
  • Publication number: 20220002491
    Abstract: The present invention relates to relates to a polymer formulation for three-dimensionally (3D) printing an article by stereolithography, the formulation comprising a functionalized polymer. The invention further relates to lithographic methods to form 3D objects that incorporate the aforementioned polymer formulation.
    Type: Application
    Filed: October 1, 2019
    Publication date: January 6, 2022
    Inventors: Joel POLLINO, Stéphane JEOL, Kermit S. KWAN, Timothy Edward LONG, Christopher Bryant WILLIAMS, Viswanath MEENAKSHISUNDARM, Nicholas Raymond CHARTRAIN, Justin SIRRINE, Katherine V. HEIFFERON
  • Patent number: 11217881
    Abstract: A spiral antenna device includes one or more conductive spiral arms that are formed on a dielectric substrate attached to a wall of a cylindrical cavity. One or more coils are formed on the wall of the cylindrical cavity and are coupled to the one or more conductive spiral arms. Starting points of the one or more conductive spiral arms are in a center region of the dielectric substrate and ending points of the one or more conductive spiral arms are electrically coupled to first ends of the one or more coils.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: January 4, 2022
    Assignee: Lockheed Martin Corporation
    Inventors: Thomas Patrick Cencich, W. Neill Kefauver, Timothy Edward Palagi
  • Publication number: 20210407810
    Abstract: A method of manufacturing an electrode structure for a device, such as a GaN or AlGaN device is described. In one example, the method includes providing a substrate (212) of GaN or AlGaN with a surface region of the GaN or AlGaN exposed through an opening (216) in a layer of silicon nitride (214) formed on the substrate. The method further includes depositing layers of W (222), in one example, or Ni (220) and W (222), in another example, on the substrate and the layer of silicon nitride using reactive evaporation and photoresist layers (230) having an undercut profile for liftoff. The method further includes removing the photoresist layers having the undercut profile, and depositing layers of WN (224) and Al over the underlying layers of W or Ni and W by sputtering.
    Type: Application
    Filed: December 6, 2019
    Publication date: December 30, 2021
    Inventors: Wayne Mack Struble, Timothy Edward Boles, Jason Matthew Barrett
  • Publication number: 20210399143
    Abstract: A monolithic, vertical, planar semiconductor structure with a number diodes having different intrinsic regions is described. The diodes have intrinsic regions of different thicknesses as compared to each other. In one example, the semiconductor structure includes an N-type silicon substrate, an intrinsic layer formed on the N-type silicon substrate, and a dielectric layer formed on the intrinsic layer. A number of openings are formed in the dielectric layer. Multiple anodes are sequentially formed into the intrinsic layer through the openings formed in the dielectric layer. For example, a first P-type region is formed through a first one the openings to a first depth into the intrinsic layer, and a second P-type region is formed through a second one of the openings to a second depth into the intrinsic layer. Additional P-type regions can be formed to other depths.
    Type: Application
    Filed: December 2, 2019
    Publication date: December 23, 2021
    Inventors: Timothy Edward Boles, James Joseph Brogle, Joseph Gerard Bukowski, Margaret Mary Barter
  • Publication number: 20210380746
    Abstract: The invention relates to an in-situ process for preparing an alkylphenol-aldehyde resin. The process comprises the step of providing a raw alkylphenol composition. The raw alkylphenol composition comprises one or more alkylphenol compounds and at least about 1 wt % phenol. Each alkylphenol compound has one or more alkyl substituents. The raw alkylphenol composition is reacted directly, without pre-purification, with one or more aldehydes to form an in-situ alkylphenol-aldehyde resin. The invention also relates to an in-situ alkylphenol-aldehyde resin formed from the in-situ process, and its use in a tackifier composition and rubber composition. The tackifier composition and rubber composition containing the in-situ alkylphenol-aldehyde resin show, inter alia, improved tack performance.
    Type: Application
    Filed: August 20, 2021
    Publication date: December 9, 2021
    Inventors: Timothy Edward BANACH, John Morgan WHITNEY, Jeffrey M. HISCOCK, Todd Scott MAKENZIE, Gennaro BARBIERO
  • Publication number: 20210374633
    Abstract: Performance quantifying and reporting for machine assets includes storing, in a work plan, asset tag assignments for a plurality of assets, and receiving location information, for example, indicative of a segment of a work cycle, being worked on by an asset. Attributes of an asset, including an inferred occurrence or non-occurrence of an asset-to-asset interaction, are based upon the location information and matching of role-based asset tags between or amongst assets. Performance history of the asset is quantified and reported based on the identified attributes for displaying, on a user interface, machine asset performance metrics.
    Type: Application
    Filed: June 1, 2020
    Publication date: December 2, 2021
    Applicant: Caterpillar Inc.
    Inventors: Arun Prasad Alayamani, Allen J DeClerk, Chad Timothy Brickner, Nicholas Adam Hanauer, Chetna Varman, Vishnu Gaurav Selvaraj, Timothy Edward Noon, Eric J. Spurgeon, Bradley K. Bomer, Umasri Devireddy
  • Publication number: 20210367084
    Abstract: A diode structure and a method of fabrication of the diode structure is described. In one example, the diode structure is a PIN diode structure and includes an N-type layer formed on a substrate, an intrinsic layer formed on the N-type layer, and a P-type layer formed on the intrinsic layer. The P-type layer forms an anode of the diode structure, and the anode is formed as a quadrilateral-shaped anode. According to the embodiments, a top surface of the anode can be formed with one or more straight segments, such as a quadrilateral-shaped anode, to reduce at least one of a thermal resistance or an electrical on-resistance. These changes, among others, can improve the overall power handling capability of the PIN diode structure.
    Type: Application
    Filed: August 6, 2021
    Publication date: November 25, 2021
    Inventors: Timothy Edward Boles, James Joseph Brogle, Andrzej Rozbicki, Belinda Simone Edmee Piernas, Daniel Gustavo Curcio, David Russell Hoag
  • Patent number: 11182526
    Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 23, 2021
    Assignee: efabless corporation
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Publication number: 20210343706
    Abstract: A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a method of manufacture of a monolithic diode limiter includes providing an N-type semiconductor substrate, providing an intrinsic layer on the N-type semiconductor substrate, implanting a first P-type region to a first depth into the intrinsic layer, implanting a second P-type region to a second depth into the intrinsic layer, and forming at least one passive circuit element over the intrinsic layer. The method can also include forming an insulating layer on the intrinsic layer, forming a first opening in the insulating layer, and forming a second opening in the insulating layer. The method can also include implanting the first P-type region through the first opening and implanting the second P-type region through the second opening.
    Type: Application
    Filed: July 13, 2021
    Publication date: November 4, 2021
    Inventors: James Joseph Brogle, Joseph Gerard Bukowski, Margaret Mary Barter, Timothy Edward Boles
  • Patent number: 11159332
    Abstract: A constrained device includes an exterior surface affixed with a public key associated with the constrained device. Alternatively, or in addition, the public key may be included in a container that stores the constrained device. The constrained device also includes memory, which stores a private key, wherein the private key corresponds to the public key that is affixed on the exterior surface of the constrained device. By displaying the public key on the constrained device, a system administrator may document the public key and related information about the device and its intended role in the network without requiring any human interface or any establishment of power or network at the installation site.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: October 26, 2021
    Assignee: Entrust, Inc.
    Inventor: Timothy Edward Moses
  • Patent number: 11155667
    Abstract: The invention relates to an in-situ process for preparing an alkylphenol-aldehyde resin. The process comprises the step of providing a raw alkylphenol composition. The raw alkylphenol composition comprises one or more alkylphenol compounds and at least about 1 wt % phenol. Each alkylphenol compound has one or more alkyl substituents. The raw alkylphenol composition is reacted directly, without pre-purification, with one or more aldehydes to form an in-situ alkylphenol-aldehyde resin. The invention also relates to an in-situ alkylphenol-aldehyde resin formed from the in-situ process, and its use in a tackifier composition and rubber composition. The tackifier composition and rubber composition containing the in-situ alkylphenol-aldehyde resin show, inter alia, improved tack performance.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: October 26, 2021
    Assignee: SI GROUP, INC.
    Inventors: Timothy Edward Banach, John Morgan Whitney, Jeffrey M. Hiscock, Todd Scott Makenzie, Gennaro Barbiero
  • Patent number: 11157300
    Abstract: In a virtualized environment where multiple guest virtual machines receive security services from multiple security virtual machines, a guest virtual machine automatically transitions to a new virtual security machine under various conditions. For example, the guest virtual machine may select a new security virtual machine when connectivity to the current security virtual machine degrades below a predetermined threshold, or in response to a request from the current security virtual machine indicating, e.g., that the current security virtual machine is about to shut down or otherwise terminate security services to the guest virtual machine.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 26, 2021
    Assignee: Sophos Limited
    Inventors: Andrew J. Thomas, Chloe Bell, Robert William Allsworth, Mark Andrew Gill, Timothy Edward Cobley, Trevor Neil McGing, Daphne Kyriaki Allamenou, Andrew Colin Piper
  • Publication number: 20210321744
    Abstract: A method of camouflaging a tonal imperfection comprising the steps of: identifying a skin tone of a user comprising a tonal imperfection; instructing the user to select a pigmented cosmetic composition adapted to camouflage the tonal imperfection based on the user's skin tone; selecting the pigmented cosmetic composition; and selectively targeting and depositing the pigmented cosmetic composition substantially only onto the tonal imperfection; wherein the pigmented cosmetic composition comprises an average composition L* value of about 10 to about 40 units greater than an average skin L* value of the user. The pigmented cosmetic composition can comprise a particular set of L*C*h* values such that when deposited onto tonal imperfections, it can result in natural, flawless looking skin, while still remaining substantially undetectable to the naked eye.
    Type: Application
    Filed: July 1, 2021
    Publication date: October 21, 2021
    Inventors: Janette Villalobos Lingoes, Thomas Elliot Rabe, Lissette D. Schorsch, Timothy Edward Nolan, Faiz Feisal Sherman, Stephan Gary Bush, Stephan James Andreas Meschkat
  • Publication number: 20210313250
    Abstract: A diode semiconductor structure is described. In one example, a diode device includes a substrate, a layer of first semiconductor material of a first doping type, a layer of intrinsic semiconductor material, and a layer of second semiconductor material of a second doping type. The diode device also includes a metal contact formed on the layer of first semiconductor material and a metal via formed from a backside of the substrate, through the substrate, and through the layer of first semiconductor material, where the metal via contacts a bottom surface of the metal contact on the layer of first semiconductor material. In this configuration, a direct electrical connection can be achieved between the backside of the substrate and the metal contact on the layer of first semiconductor material without the need for an additional metal connection, such as a metal air bridge, to the metal contact.
    Type: Application
    Filed: April 2, 2020
    Publication date: October 7, 2021
    Inventors: Andrzej Rozbicki, Belinda Simone Edmee Piernas, David Russell Hoag, James Joseph Brogle, Timothy Edward Boles
  • Publication number: 20210308469
    Abstract: Systems, devices and methods to facilitate wireless interaction between an implantable therapy delivery device and an external transmitter device are provided. In an example, the systems, devices, and methods discussed herein include or use a garment for receiving and positioning an external transmitter device proximal to an implanted device, and the external transmitter device includes a midfield device configured to provide one or more signals to manipulate evanescent fields outside of tissue to generate a propagating and focused field in the tissue. In an example, the garment includes a receptacle configured to receive and retain the external transmitter device near a tissue interface, and the garment further includes a dielectric portion provided between the receptacle and the tissue interface. In an example, the dielectric portion has a relative permittivity that is approximately the same as the relative permittivity of air.
    Type: Application
    Filed: September 5, 2019
    Publication date: October 7, 2021
    Inventors: Brad Holinski, Alexander Yeh, Elia Junco, Timothy Edward Ciciarelli
  • Patent number: 11127737
    Abstract: A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a diode limiter semiconductor structure have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. The thin intrinsic region PIN diode can be optimized for low level turn on and flat leakage, and the thick intrinsic region PIN diode can be optimized for low capacitance, good isolation, and high incident power levels. This configuration is not limited to two stage solutions, as additional stages can be used for higher incident power handling.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: September 21, 2021
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: James Joseph Brogle, Joseph Gerard Bukowski, Margaret Mary Barter, Timothy Edward Boles