Abstract: The present invention relates in general to an integrated circuit timer system, and more particularly to an integrated circuit timer system having at least one global communication bus conductor for transferring information between local buses. Referring to FIGS. 1 and 10, a global channel communication bus (200) is used to communicate information between channels (204-206) which are coupled to different pin/status buses (216-218). The purpose of the global channel communication bus (200) is to synchronously transfer information between channels in different I/O control modules (IOCMs 25-29), and to synchronously transfer information between channels (e.g. 204-206) within an IOCM (e.g. 27) that are coupled to different pin/status buses (e.g. 216 and 217). In addition, in some embodiments, the global channel communication bus (200) can provide and receive information from external to input/output integrated circuit (22) by way of integrated circuit pins (223).

Abstract: Referring to FIGS. 20-24, in one embodiment, data can be transferred from the data register of a top adjacent timer channel (e.g. 400 in FIG. 20) to the data register of the timer channel itself (401), and from the data register of the timer channel itself (401) to the data register of the bottom adjacent timer channel (402). By programming control register bits (e.g. DVB bits 425-426, DTC bits 423-424, and DTS bits 427-428 in FIG. 21) of selected timer channels (401) to perform these inter-channel data transfers, both stacks and FIFO structures can be formed and used. Stack and FIFO data storage structures can reduce the frequency of service required by the timer channels (400-402), and thus reduce the number of interrupts which must be responded to by a CPU (13 in FIG. 1).

Abstract: I/O control modules (IOCMs 25-29) include pin/status buses (75-77) which allow simultaneity of control among the channels (e.g. 58) coupled to the same pin/status bus (e.g. 76). Thus, the operation of channels (e.g. 58) can be synchronized with each another. Pin/status buses (75-77) are modular in that they can be extended or alternately segmented to create separate buses carrying different signals. In one embodiment, each end of pin/status bus (75-77) is delineated by a pin control channel (PCCs 51-53). Pin/status buses (75-77) may be used to transfer event information between channels within an IOCM (e.g. IOCM 25), to transfer event information from one IOCM (e.g. 25) to a different IOCM (e.g. 26), and to transfer pin information between integrated circuit pins (31-35) and one or more channels in IOCMs (25-29).