Abstract: A disk drive is disclosed comprising a disk, a spindle motor operable to rotate the disk, a head actuated over the disk, an interface operable to receive a host supply voltage, and a capacitor. The host supply voltage is used to charge the capacitor to a capacitor voltage higher than the host supply voltage. During a power failure, the host supply voltage stops charging the capacitor, and a motor supply voltage is generated from the spindle motor. The capacitor voltage is used to operate control circuitry, and when the capacitor voltage decays below the motor supply voltage, the motor supply voltage charges the capacitor.

Abstract: A disk drive is disclosed comprising a disk, a spindle motor operable to rotate the disk, a head actuated over the disk, an interface operable to receive a host supply voltage, and a capacitor. The host supply voltage is used to charge the capacitor to a capacitor voltage higher than the host supply voltage. During a power failure, the host supply voltage stops charging the capacitor, and a motor supply voltage is generated from the spindle motor. The capacitor voltage is used to operate control circuitry, and when the capacitor voltage decays below the motor supply voltage, the motor supply voltage charges the capacitor.

Abstract: A data storage device is disclosed comprising a first disk surface, a first head, and a first microactuator configured to actuate the first head over the first disk surface. The first microactuator is configured into a first sensor, and a first load operation is executed to load the first head over the first disk surface. A fly height instability of the first head is detected during the first load operation based on a first sensor signal generated by the first microactuator.

Abstract: A digital device is disclosed comprising a memory, a microprocessor operable to access the memory, and a voltage regulator for ramping an output voltage supplied to the memory during a startup operation. During the startup operation, control circuitry monitors the output voltage, and when the output voltage remains above a first threshold for a predetermined interval, sets a flag. Thereafter, the voltage regulator is enabled to ramp the output voltage after the predetermined interval.

Abstract: A power control device comprising an always-on-domain (AOD) which includes control logic circuitry for controlling power from a power source, load switches, bias current generators. The power control device also includes, outside of the AOD, functional blocks. The control logic circuitry is configured to receive a signal to go into a lower power state, initiate a shut-down sequence of the load switches and the bias current generators of the AOD, to disable circuitry outside of the AOD, including the functional blocks of the power control device and loads controlled by the power control device, and operate in a low power state to detect a wake-up signal. The shut-down sequence may additionally include sequencing off voltage regulators outside of the AOD and a clock control inside the AOD.

Abstract: A disk drive is disclosed comprising a microactuator configured to actuate a head over a disk, and control circuitry comprising a first digital accumulator responsive to a first register. The first digital accumulator generates at least one of a velocity command and a position command for the microactuator, and the control circuitry configures the first register in order to limit at least one of a velocity and an acceleration of the microactuator.

Abstract: A data storage device is disclosed comprising a head actuated over a disk, and a spindle motor configured to rotate the disk, wherein the spindle motor comprises a plurality of windings. A commutation controller is configured to commutate the windings based on a commutation sequence. Compensation values are generated based on: A1 sin ?1t+B1 cos ?lt where A1 and B1 are adaptable coefficients and ?1 represents a first frequency based on a first mechanical parameter of the spindle motor. The compensation values are used to drive the commutation sequence of the commutation controller.

Abstract: A disk drive is disclosed comprising a head actuated over a disk, and control circuitry comprising a first shock detector and a second shock detector. A first number of shock events is detected based on the first shock detector, and when the first number of shock events exceeds an upper event threshold, a sensitivity of the first shock detector is decreased. After decreasing the sensitivity of the first shock detector, a second number of shock events is detected based on the second shock detector operating at a higher sensitivity than the first shock detector. When the second number of shock events falls below a lower event threshold, the sensitivity of the first shock detector is increased.

Abstract: A disk drive is disclosed comprising a head actuated over a disk, wherein the head comprises a dynamic fly height (DFH) actuator. The disk drive further comprises an electrical heating element, and control circuitry operable to select an operating control signal applied to the DFH actuator by heating the electrical heating element for a first heating time, measuring a rate of temperature change of the electrical heating element, and selecting the operating control signal applied to the DFH actuator in response to the rate of temperature change.

Abstract: A data storage device (DSD) is disclosed comprising a non-volatile memory (NVM), and control circuitry comprising a first voltage regulator having a first output operable to generate a first current, and a second voltage regulator having a second output operable to generate a second current. When in an independent mode, the first current is operable to supply a first load independent of the second current, and the second current is operable to supply a second load independent of the first current. When in a parallel mode, the second output is coupled to the first output in order to increase the first current supplied to the first load and decrease the second current supplied to the second load.

Abstract: A data storage device is disclosed comprising a head actuated over a disk, a spindle motor configured to rotate the disk, and control circuitry configured to perform a power fail operation by boosting a power voltage generated based on the spindle motor to generate a boosted voltage, controlling an operation of the data storage device using the boosted voltage, and when the power voltage falls below a threshold, reducing the boosting so as to reduce the boosted voltage.

Abstract: A data storage device is disclosed comprising a disk, a head, and a microactuator configured to actuate the head over the disk. The data storage device further comprises control circuitry comprising a digital-to-analog converter (DAC) configured to generate a control signal applied to the microactuator. The control circuitry measures an operating temperature and then adjusts a range of the DAC based on the measured operating temperature.

Abstract: A data storage device is disclosed comprising a non-volatile memory and control circuitry comprising an interface operable to receive a supply voltage, and a capacitor. An operating voltage regulator converts the supply voltage into an operating voltage used to operate the non-volatile memory. The supply voltage is used to charge the capacitor to a capacitor voltage higher than the supply voltage, and during a power failure, a backup voltage regulator converts the capacitor voltage into a backup voltage substantially equal to the supply voltage. The operating voltage regulator converts the backup voltage into the operating voltage used to operate the non-volatile memory.

Abstract: A voltage booster is disclosed comprising an input for receiving an input voltage Vin, a first charging capacitor C1, a second charging capacitor C2, and an output capacitor Cout. The output capacitor Cout is charged to four times Vin by connecting C1 in parallel with Vin to charge C1 to Vin, after charging C1 to Vin, connecting C2 in parallel with Vin plus C1 to charge C2 to twice Vin, after charging C2 to twice Vin, connecting C1 in parallel with Vin to recharge C1 to Vin, and after recharging C1, connecting Cout in parallel with Vin plus C1 plus C2 to charge Cout to four times Vin.

Abstract: A disk drive is disclosed comprising a disk, a spindle motor operable to rotate the disk, a head actuated over the disk, an interface operable to receive a host supply voltage, and a capacitor. The host supply voltage is used to charge the capacitor to a capacitor voltage higher than the host supply voltage. During a power failure, the host supply voltage stops charging the capacitor, and a motor supply voltage is generated from the spindle motor. The capacitor voltage is used to operate control circuitry, and when the capacitor voltage decays below the motor supply voltage, the motor supply voltage charges the capacitor.

Abstract: Self-heating integrated circuits are provided. In one embodiment, a self-heating integrated circuit comprises a drive circuit configured to drive a device and a controller configured to selectively operate the drive circuit in a first mode or a second mode. In the first mode, the controller is configured to operate the drive circuit to drive the device and, in the second mode, the controller is configured to operate the drive circuit to heat the integrated circuit to a target temperature.

Abstract: A hysteretic voltage regulator is disclosed comprising an inductor having a first end and a second end, wherein the second end is connected to an output capacitor in shunt with a load. A switch connects the first end of the inductor to a supply voltage when an output voltage across the load falls below a reference voltage, and disconnects the first end of the inductor from the supply voltage when a current flowing through the output capacitor rises above a reference current.

Abstract: A soft start sequencer is disclosed for starting a plurality of voltage regulators, the soft start sequencer comprising a first clock for clocking a plurality of soft start circuits, wherein each soft start circuit for ramping a reference signal from a first value to a second value over a ramp time after a delay time. Each soft start circuit comprises a divider operable to divide the first clock by an integer N to generate a second clock, a first counter clocked by the first clock, the first counter operable to time the delay time, and a second counter clocked by the second clock, the second counter operable to time the ramp time after the delay time.

Abstract: A disk drive is disclosed comprising a disk, a head for writing data to the disk, and control circuitry coupled to the head, the control circuitry comprising a signal amplifier outputting a first signal comprising an offset voltage, the control circuitry operable to determine a state signal based on comparing the first signal to a reference signal, increase a M-bit digital count value in response to a first state of the state signal, decrease the M-bit digital count value in response to a second state of the state signal, and determine a first analog signal based on N bits of the digital count value, wherein the first analog signal adjusts the offset voltage and M>N.

Abstract: A disk drive is disclosed comprising a disk, a head actuated radially over the disk, and control circuitry including a shock detector. The control circuitry is operable to detect a resonant frequency amplitude (RFA) of the shock detector, adjust the shock detector in response to the RFA, and take protective action in response to the shock detector.