Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.

Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.

Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.

Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.

Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.

Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.

Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.

Abstract: In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model.

Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.

Abstract: A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.

Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.

Abstract: A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

Abstract: The present invention provides a new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

Abstract: An apparatus and method for allowing for dynamic wordline repair in a clock running system in addition to allowing for programmable fuse support of combined Array Built-In Self-Test (ABIST) and Logic Built-In Self-Test (LBIST) testing. The method makes use of programmable fuses which contain Level Sensitive Scan Design (LSSD) latches which also have a system port. The system port allows for simpler reading of the fuses as well as for the dynamic updates of the programmable fuses for wordline and other repairs.

Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

Abstract: A method of self-synchronizing clocks in a multiple chip system, by assigning one chip as the master chip and the other chips as slave chips. A training signal is sent from master chip to the slave chips to determine the latency from the master chip to a slave chip, and then a synchronization signal is sent out to synchronize the “time zero” of the chips.

Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal, the clock high and clock low signal having patterns derived from a waveform of a target divided ratio clock and the clock high and clock low signals have patterns that match the targeted divided clock frequency and duty cycle. Local pass gate are provided for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

Abstract: A method and apparatus for operating a clock in a processor having asymmetrically mirrored base-mirror units is disclosed. The method includes initializing a base-unit and a mirror-unit of the processor to the same state, and starting the mirror-unit-clock one clock cycle later than the base-unit-clock.