Abstract: An acoustic/video processing stack of a plurality of substantially identical acoustic/video processing stacks is provided for attachment to a processing stack backplane and which together generate a VGA signal for display of a three-dimensional acoustic image. The acoustic/video processing stack includes a two-dimensional array of transducer elements, a companion chip block coupled to and adapted to transceive acoustic signals under a time-division multiplexed format through the transducer elements and to provide a portion of the VGA signal together generated by the plurality of acoustic/video processing stacks and a backing block disposed between the two-dimensional array and companion chip block and adapted to acoustically isolate the two-dimensional transducer array from the companion chip block, said companion chip block and backing block being of a size and diameter substantially the same as the two-dimensional transducer array.

Abstract: A self calibrating current mirror circuit has a curent mirror input for receiving an input current, and a current mirror output for providing an output current. The circuit utilizes a comparator, a charge pump and a MOS transistor having a drain connected to pair of transfer gates. In a first mode of operation, the current of the MOS transistor is switched to the current mirror input for calibration. The comparator provides a signal to the charge pump to increase or to decrease the gate voltage of the MOS transistor. In a second mode of operation the current of the MOS transistor is switched to the current mirror output. A plurality of self calibrating current mirror stages are used to obtain a current mirror that provides an output with multiple current levels, for use as a switched current digital to analog converter (DAC).

Abstract: A tunable oscillator includes an input for receiving an input signal from a source of precision frequency such as a CMOS quartz crystal oscillator. The tunable oscillator converts the frequency of the input signal to a first current using a frequency to current converter. The current produced is proportional to a first capacitor, C1. The first current is replicated to produce a subsequent current using a current mirror structure. The subsequent current is then used to generate a periodic signal using a current to frequency converter. The output frequency of the current to frequency converter is inversely proportional to a second capacitor, C2. As such the output frequency of the tunable oscillator is tunable by changing the value of the capacitance ratio C1/C2. The invention is suitable for applications that require a precision tunable source of frequency such as automated test equipment (ATE) and electrical instrumentation.

Abstract: A multiple stage tracking filter includes a self-calibrating RC oscillator, a resistor connected to the self-calibrating RC oscillator and a capacitor connected to the self-calibrating RC oscillator. The filter further includes a switched capacitor filter element connected to the self-calibrating RC oscillator. The switched capacitor filter elements include a switch which is controlled by a timing signal from the self-calibrating RC oscillator. A method of filtering a signal includes the steps of operating a self-calibrating RC oscillator to generate a timing signal, tuning a plurality of cascaded filter elements with the generated timing signal and passing a signal through the plurality of tuned cascaded filter elements.

Abstract: A clock overdrive function is provided which advantageously facilitates testing of circuits incorporating timing circuits. The clock overdrive function allows a tester to furnish a clock pulse timing reference to drive a circuit containing a system clock, thereby overdriving the system clock signal. Overdriving of the system clock signal allows precise control of circuit timing. A method of overdriving a system clock signal includes the steps of forming a low reference voltage and a high reference voltage, applying a timing signal having a timing signal voltage at an external pin, comparing the timing signal voltage at the external pin to the low reference voltage and the high reference voltage, driving the circuit with the system clock timing signal when the timing signal voltage at the external pin is less than the low reference voltage and driving the circuit with the timing signal at the external pin, otherwise.

Abstract: A timer initialization circuit is used to stabilize a timing signal of a system timed using a core oscillator. The timer initialization circuit includes a circuit which disables the core oscillator during a power-down mode and re-enables the core oscillator upon termination of the power-down mode. The timer initialization circuit also includes a circuit which stores an indication of an oscillation frequency at which the circuit operates immediately preceding the power-down mode.

Abstract: An RC oscillator includes an RC network for forming a time constant equal to the RC product. However, this RC time constant is not used in the manner of a typical RC network to set the frequency of oscillation. Instead, the RC oscillator disclosed herein includes a separate oscillator, such as a voltage-controlled oscillator (VCO), and uses the RC time constant to compare with the oscillator-generated period and to adjust the frequency of the overall RC oscillator circuit in accordance with the comparison. The RC oscillator is self-calibrating.

Abstract: A component detector circuit operates to detect the presence or absence of a circuit component, such as an external component. A resistor detecting circuit includes a biasing circuit connected to the resistor. The biasing circuit generating a bias current. The resistor detecting circuit also includes a bias current threshold detector connected to the biasing circuit and a circuit connected to the bias current threshold detector which generates a signal indicative that the bias current is lower than threshold. A capacitor detecting circuit includes a circuit connected to a resistor and configured to be connected to a capacitor which establishes a time constant proportional to an RC product of the resistor and capacitor.

Abstract: A low power RC oscillator includes a low power bias circuit and an RC network. The RC network is used to form a time constant equal to the RC product. However, this RC time constant is not used in the manner of a typical RC network to set the frequency of oscillation. Instead, the RC oscillator disclosed herein includes a separate oscillator, such as a voltage-controlled oscillator (VCO), and uses the RC time constant to compare with the oscillator-generated period and to adjust the frequency of the overall RC oscillator circuit in accordance with the comparison. The RC oscillator is self-calibrating.

Abstract: A digitally-tuned oscillator (DTO) includes a digital-to-analog converter (DAC) and an RC oscillator. The RC oscillator includes an RC circuit for forming a time constant equal to the RC product. However, this RC time constant is not used in the manner of a typical RC network to set the frequency of oscillation. Instead, the RC oscillator disclosed herein includes a separate oscillator, such as a voltage-controlled oscillator (VCO), and uses the RC time constant to compare with the oscillator-generated period and to adjust the frequency of the overall RC oscillator circuit in accordance with the comparison. The RC oscillator is self-calibrating.

Abstract: A monolithic frequency converter using a feedback control loop generates a source of synthesized frequency signals over a wide dynamic range based on a timing source such as a crystal oscillator or an external frequency source. The frequency converter includes a controlled oscillator, a frequency counter, a timing signal generator and, connected between the frequency counter and the controlled oscillator, a digital to analog converter and a difference integrator. The controlled oscillator generates a clock signal at a frequency controlled by an electrical signal. The difference integrator is connected to an input signal terminal and connected to the timing signal generator. The difference integrator determines a difference signal between the input signal and a signal operated upon by the digital to analog converter and integrates the difference signal under control of a timing signal generated by the timing signal generator.

Abstract: A comparator which is used to compare two analog voltages and provide a single ended output comprises three CMOS differential amplifiers. The use of three differential amplifiers provides improved matching of input capacitance, and a reduction in propagation delay over prior art use of a single differential amplifier. The comparator may be adopted for use in certain CMOS processes to extend the maximum operating voltage by limiting the internal node voltages otherwise subject to damage from impact ionization. An alternative embodiment is disclosed for comparing two analog voltages that are outside the power supply voltage range.

Abstract: A stability-compensated, integrated-circuit operational amplifier has an open-loop gain versus frequency characteristic which provides stable and accurate closed-loop operation in numerous overall circuits including a CMOS circuit for producing a precision current as a reference to a digital-to-analog converter. The operational amplifier comprises an inverting node and a non-inverting node, and CMOS circuitry defining two differential amplifiers. Each differential amplifier is connected to the inverting node and the non-inverting node. The first differential amplifier has an output node, and produces on the output node an output potential that defines an output signal having a magnitude that is a function of the magnitude of the difference between a first potential at the inverting node and a second potential at the non-inverting node. The second differential amplifier is also connected to the inverting node and the non-inverting node. The second differential amplifier produces a compensation signal.

Abstract: A DAC embodied in a CMOS integrated circuit converts a multi-bit digital signal to an analog-current signal. A higher-order portion of the digital signal, e.g., the most significant 5 bits of a byte, are decoded separately from the lower-order portion, e.g., the 3 least significant bits. The DAC includes circuitry for producing a first bias voltage, a first set of current sources each biased by the first bias voltage to produce a switchable current having a unit magnitude, and switching circuitry controlled by the decoded lower-order portion to cause a selected number of the unit-magnitude currents to contribute to the analog-current signal.

Abstract: A method for controlling a programmable source of a plurality of string of clock signals, a program is stored with a plurality of different indications of desired frequencies, each indication corresponding to one of the strings of clock signals. The frequency of each of a plurality of oscillator is controlled by the memory content of a separate memory for each oscillator. The content of each memory is adjusted in accordance with the actual frequency of each string, the frequency indicated by the corresponding indication of a desired frequency and a reference.

Abstract: The transient noise generated at the output drivers of an integrated circuit chip is reduced by maintaining an increasing ramp shaped current through each output driver during the entire transition interval between binary states of a capacitive load. A capacitor fed by a fixed current source is connected across the input of each output driver stage. The fixed current source and capacitor are so selected as to generate across the input of each output driver stage a linear ramp shaped control voltage that regulates the charging/discharging current through the output driver stage and package inductance in the described manner. A specially designed bias circuit reduces the sensitivity of the resulting transient noise to process variations and operating conditions. A feedback connection from the package inductance to the bias control circuit for the fixed current source adjusts the fixed current inversely with the transient noise.

Abstract: A Schmitt trigger having first and second complementary switches is biased to exhibit hysteresis, switching at a high threshold level when the input signal increases, and switching at a low threshold level when the input decreases. The source driver for the Schmitt trigger is coupled to the input of at least one of the complementary switches by transition circuitry, such that the signal level representing one binary value is shifted closer to the level of the power supply voltage corresponding to such binary value without changing the logical value of the signal from the source driver. In one embodiment, the first inverter is a MOS transistor, the threshold level of which is set by a bias voltage applied to the gate of another MOS transistor. The second inverter is a pair of complementary CMOS transistors. In another embodiment, the first inverter also comprises a pair of complementary CMOS transistors. The threshold level is set by selecting the W/L ratio of the CMOS transistors of the first inverter.

Abstract: A circuit is provided for realizing multiple precision resistor elements on an integrated circuit by sensing a reference resistor. The circuit contains a first current source which passes a first current through a reference resistor located either on or off of the integrated circuit to generate a reference voltage. The reference voltage is applied to the inverting input of a precision high gain operational amplifier. A second current source is connected to the drain of a first MOS transistor operating in its ohmic region. The second current source is also connected to the non-inverting input of the high gain operational amplifier. The output of the operational amplifier is electrically connected to the gate of the first and second MOS transistors. In operation, a precision resistance is developed across the second MOS transistor which is equal to or some determinable multiple of the resistance of the reference precision resistor located on or off chip.

Abstract: A Schmitt trigger circuit with independently biased threshold sections includes a drive disabling switch for blocking one of the threshold sections from driving a logic node toward a predetermined logic state. The drive disabling switch is selectively operated so that unidirectional sensitivity to the crossing of a threshold level belonging to its corresponding one threshold section is obtained.

Abstract: The present invention provides an apparatus and method for allowing an electronic device to drive large values of load capacitance without generating high levels of transient noise. Means are provided for passing a first current through the parasitic inductance of the integrated circuit prior to the activation of the output driver, presoaking the parasitic inductance. Thereafter, when the output driver is activated and the load capacitance discharges through the inductance of the integrated circuit, the first current is removed from as the current from the load capacitor replaces it. Since an initial level of current existed through the inductance, the rate of change of current passing through the inductance during activation of the output driver is maintained approximately constant, thereby reducing the level of transient noise generated by the electronic device.