Abstract: A device tester, such as a memory tester, is electrically interfaced to a device under test, such as a memory die, by means of an improved interface system. The interface system includes an array of coaxial cables for making electrical connection to the test circuits of the device tester by means of coaxial connections at the tester ends. The coaxial cables are fitted at their other ends with slidable two-conductor connector receptacles which make connections to fixed male pins of spring loaded feedthrough connectors passing through a mother board. The spring loaced pins of the feedthroughs make electrical contact to eyelets terminals of strip-line circuits on a probe card (daughter board) terminating on an array of flexible probes for probing the memory die under test. As an alternative, the eyelet terminals of the daughter board are connected to sockets to receive the device under test.

Abstract: A memory tester is disclosed for testing a matrix of memory elements, such matrix having spare rows and columns of memory elements to be used for repair of the memory under test. The memory tester tests the memory matrix to derive failure data and stores the failure data in corresponding rows and columns in a second memory matrix. Failure data in the second memory is scanned first by row and when the number of failures in any row exceeds the number of spare columns that row is flagged for replacement. Next, the columns of failure data are scanned and when the number of failures in any column exceeds the number of spare rows, that column is flagged for replacement. During the scan of the columns, previously flagged rows are masked such that failures which are to be repaired are not counted.