Patents by Inventor Timothy Harrison Daubenspeck
Timothy Harrison Daubenspeck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9105465Abstract: The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.Type: GrantFiled: March 22, 2011Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Timothy Harrison Daubenspeck, Jeffrey P. Gambino, Christopher David Muzzy, Wolfgang Sauter, Timothy Dooling Sullivan
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Patent number: 8819933Abstract: A method for forming an electrical structure. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.Type: GrantFiled: December 1, 2010Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Christopher David Muzzy, Wolfgang Sauter
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Patent number: 8592976Abstract: A structure. The structure includes: a first dielectric layer which includes a top dielectric surface; an electrically conductive line on the first dielectric layer; a second dielectric layer on the first dielectric layer and the electrically conductive line; a ball-limiting-metallurgy (BLM) region on the second dielectric layer and the electrically conductive line such that the BLM region is electrically connected to the electrically conductive line; and a solder ball on the BLM region. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface and is entirely in the BLM region does not exceed a pre-specified maximum value, wherein the pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface.Type: GrantFiled: September 14, 2012Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Timothy Harrison Daubenspeck, Wolfgang Sauter, Timothy Dooling Sullivan
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Patent number: 8575007Abstract: The invention includes embodiments of a method for designing a flip chip and the resulting structure. The starting point is a flip chip with a semiconductor substrate, one or more wiring levels, and a plurality of I/O contact pads (last metal pads/bond pads) for receiving and sending electrical current. There is also a plurality of C4 bumps for connecting the I/O contact pads to another substrate. Then it is determined which of the C4s of the plurality of C4 bumps have a level of susceptibility to electromigration damage that meets or exceeds a threshold level of susceptibility, and in response, plating a conductive structure with a high electrical current carrying capacity (such as a copper pillar, copper pedestal, or partial copper pedestal) onto the corresponding I/O contact pads and adding a solder ball to a top portion of the conductive structure. The resulting structure is a flip chip wherein only a select few C4 bumps use enhanced C4s (such as copper pedestals) reducing the chance of defects.Type: GrantFiled: March 28, 2011Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Timothy Harrison Daubenspeck, Jeffrey P. Gambino, Christopher David Muzzy, Wolfgang Sauter, Thomas Anthony Wassick
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Patent number: 8361598Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate, a first dielectric layer, an underfill layer, a first solder structure, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The first solder structure is formed within the first opening and over a portion of the top surface of said first dielectric layer. The second substrate is formed over and in contact with the underfill layer.Type: GrantFiled: January 6, 2011Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Christopher David Muzzy, Wolfgang Sauter
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Publication number: 20130008699Abstract: A structure. The structure includes: a first dielectric layer which includes a top dielectric surface; an electrically conductive line on the first dielectric layer; a second dielectric layer on the first dielectric layer and the electrically conductive line; a ball-limiting-metallurgy (BLM) region on the second dielectric layer and the electrically conductive line such that the BLM region is electrically connected to the electrically conductive line; and a solder ball on the BLM region. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface and is entirely in the BLM region does not exceed a pre-specified maximum value, wherein the pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: International Business Machines CorporationInventors: Charles L. Arvin, Timothy Harrison Daubenspeck, Wolfgang Sauter, Timothy Dooling Sullivan
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Patent number: 8338286Abstract: A method for reducing stress on under ball metallurgy (UBM) is disclosed. A collar is disposed around the ball to provide support, and prevent solder interaction in the undercut areas of the UBM. In one embodiment, the collar is comprised of photosensitive polyimide.Type: GrantFiled: October 5, 2010Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: Eric David Perfecto, Harry David Cox, Timothy Harrison Daubenspeck, David L. Questad, Brian Richard Sundlof
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Patent number: 8299611Abstract: A solder ball structure and a method for forming the same. The structure includes (i) a first dielectric layer which includes a top dielectric surface, (ii) an electrically conductive line, (iii) a second dielectric layer, (iv) a ball-limiting-metallurgy (BLM) region, and (v) a solder ball. The BLM region is electrically connected to the electrically conductive line and the solder ball. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface of the first dielectric layer and is entirely in the BLM region does not exceed a pre-specified maximum value. The pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface of the first dielectric layer.Type: GrantFiled: August 26, 2009Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Timothy Harrison Daubenspeck, Wolfgang Sauter, Timothy Dooling Sullivan
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Publication number: 20120248604Abstract: The invention includes embodiments of a method for designing a flip chip and the resulting structure. The starting point is a flip chip with a semiconductor substrate, one or more wiring levels, and a plurality of I/O contact pads (last metal pads/bond pads) for receiving and sending electrical current. There is also a plurality of C4 bumps for connecting the I/O contact pads to another substrate. Then it is determined which of the C4s of the plurality of C4 bumps have a level of susceptibility to electromigration damage that meets or exceeds a threshold level of susceptibility, and in response, plating a conductive structure with a high electrical current carrying capacity (such as a copper pillar, copper pedestal, or partial copper pedestal) onto the corresponding I/O contact pads and adding a solder ball to a top portion of the conductive structure. The resulting structure is a flip chip wherein only a select few C4 bumps use enhanced C4s (such as copper pedestals) reducing the chance of defects.Type: ApplicationFiled: March 28, 2011Publication date: October 4, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Harrison Daubenspeck, Jeffrey P. Gambino, Christopher David Muzzy, Wolfgang Sauter, Thomas Anthony Wassick
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Publication number: 20120241916Abstract: The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.Type: ApplicationFiled: March 22, 2011Publication date: September 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Harrison Daubenspeck, Jeffrey P. Gambino, Christopher David Muzzy, Wolfgang Sauter, Timothy Dooling Sullivan
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Publication number: 20120126405Abstract: Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad.Type: ApplicationFiled: January 30, 2012Publication date: May 24, 2012Applicant: International Business Machines CorporationInventors: Timothy Harrison Daubenspeck, Timothy D. Sullivan
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Publication number: 20120083114Abstract: A method for reducing stress on under ball metallurgy (UBM) is disclosed. A collar is disposed around the ball to provide support, and prevent solder interaction in the undercut areas of the UBM. In one embodiment, the collar is comprised of photosensitive polyimide.Type: ApplicationFiled: October 5, 2010Publication date: April 5, 2012Applicant: International Business Machines CorporationInventors: ERIC DANIEL PERFECTO, Harry David Cox, Timothy Harrison Daubenspeck, David L. Questad, Brian Richard Sundlof
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Patent number: 8138602Abstract: Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad.Type: GrantFiled: September 20, 2010Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Timothy Harrison Daubenspeck, Timothy D. Sullivan
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Patent number: 7939390Abstract: A semiconductor structure formation method and operation method. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball.Type: GrantFiled: April 23, 2010Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Stephen P. Ayotte, Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Christopher David Muzzy, Wolfgang Sauter
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Publication number: 20110100685Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate, a first dielectric layer, an underfill layer, a first solder structure, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The first solder structure is formed within the first opening and over a portion of the top surface of said first dielectric layer. The second substrate is formed over and in contact with the underfill layer.Type: ApplicationFiled: January 6, 2011Publication date: May 5, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Christopher David Muzzy, Wolfgang Sauter
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Patent number: 7935408Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate, first dielectric layer, an underfill layer, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The underfill layer is formed over the top surface of the first dielectric layer and within the first opening. The second substrate is formed over and in contact with the underfill layer.Type: GrantFiled: October 26, 2007Date of Patent: May 3, 2011Assignee: International Business Machines CorporationInventors: Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Christopher David Muzzy, Wolfgang Sauter
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Publication number: 20110072656Abstract: A method for forming an electrical structure. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.Type: ApplicationFiled: December 1, 2010Publication date: March 31, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Christopher David Muzzy, Wolfgang Sauter
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Patent number: 7911803Abstract: An electrical structure and method of forming. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.Type: GrantFiled: October 16, 2007Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Christopher David Muzzy, Wolfgang Sauter
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Patent number: 7871920Abstract: Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate.Type: GrantFiled: April 19, 2010Date of Patent: January 18, 2011Assignee: International Business Machines CorporationInventors: Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Christopher David Muzzy, Wolfgang Sauter
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Publication number: 20110006421Abstract: Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad.Type: ApplicationFiled: September 20, 2010Publication date: January 13, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Harrison Daubenspeck, Timothy D. Sullivan