Abstract: Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing.

Abstract: Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS.

Abstract: A method and system for high speed on chip testing for quality assurance. A multi-core system on a chip has a plurality of processing cores. The cores act as transaction agents with an auto-response unit fabricated on the chip at a chip boundary, the auto-response unit to provide a deterministic return value based on a logical address of a received read request.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing.

Abstract: A method, used with dual-fuel engine, of controlling the amount of gaseous fuel delivered to the engine. At operating conditions that result in an equivalence ratio below a predetermined threshold (which typically occur at mid or part loads), it is determined whether better performance and/or lower emissions can be achieved by reducing gaseous fuel to some cylinders and increasing gaseous fuel to others. Typically, the gaseous fuel is reduced to zero to a number of cylinders and increased to others, with the increase resulting in an equivalence ratio that will provide improved emissions and efficiency and the desired engine output.

Abstract: A method and system for high speed on chip testing for quality assurance. A multi-core system on a chip has a plurality of processing cores. The cores act as transaction agents with an auto-response unit fabricated on the chip at a chip boundary, the auto-response unit to provide a deterministic return value based on a logical address of a received read request.

Abstract: A method, used with dual-fuel engine, of controlling the amount of gaseous fuel delivered to the engine. At operating conditions that result in an equivalence ratio below a predetermined threshold (which typically occur at mid or part loads), it is determined whether better performance and/or lower emissions can be achieved by reducing gaseous fuel to some cylinders and increasing gaseous fuel to others. Typically, the gaseous fuel is reduced to zero to a number of cylinders and increased to others, with the increase resulting in an equivalence ratio that will provide improved emissions and efficiency and the desired engine output.

Abstract: A method, used with dual-fuel engine, of controlling the amount of diesel fuel delivered to the engine. The method compensates for the poor transient response of gaseous fueling. A controller receives a signal from the operator of the engine representing a desired torque, and based on this signal, determines a desired intake manifold state. It generates commands to various actuators to control the intake air and the intake gaseous fuel such that the desired intake manifold state will occur. The controller also receives sensor data from which the current in-cylinder state can be measured or estimated. It determines a current amount of diesel fuel based on the desired torque, the engine speed and the current in-cylinder state, and generates a diesel fueling command.

Abstract: A method, used with dual-fuel engine, of controlling the amount of diesel fuel delivered to the engine. The method compensates for the poor transient response of gaseous fueling. A controller receives a signal from the operator of the engine representing a desired torque, and based on this signal, determines a desired intake manifold state. It generates commands to various actuators to control the intake air and the intake gaseous fuel such that the desired intake manifold state will occur. The controller also receives sensor data from which the current in-cylinder state can be measured or estimated. It determines a current amount of diesel fuel based on the desired torque, the engine speed and the current in-cylinder state, and generates a diesel fueling command.

Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

Abstract: A persistent cacheable high volume manufacturing (HVM) initialization code is generally presented. In this regard, an apparatus is introduced comprising a processing unit, a unified cache, a unified cache controller, and a control register to selectively mask off access by the unified cache controller to portions of the unified cache. Other embodiments are also described and claimed.

Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

Abstract: A persistent cacheable high volume manufacturing (HVM) initialization code is generally presented. In this regard, an apparatus is introduced comprising a processing unit, a unified cache, a unified cache controller, and a control register to selectively mask off access by the unified cache controller to portions of the unified cache. Other embodiments are also described and claimed.

Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.