Patents by Inventor Timothy J. Canales

Timothy J. Canales has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010038304
    Abstract: A storage cell of an integrated circuit is operable in a radiation environment to capture and store at predetermined time intervals a time sample of a data input signal. A signal representative of the stored data sample for each time interval is generated at an output of the storage cell. The storage cell comprises at least three data capturing circuits, each operable to capture and store a time sample of the data input signal at each predetermined time interval, the stored data sample of each circuit being generated correspondingly at an output thereof. Coupled to the outputs of the data capturing circuits is a circuit for generating a signal representative of a stored data sample selected from at least two of the circuit outputs. Also coupled to the data capturing circuits is a circuit for causing each data capturing circuit to capture a different time sample of the input data signal from the other data capturing circuits over each predetermined time interval.
    Type: Application
    Filed: April 9, 2001
    Publication date: November 8, 2001
    Inventors: Arthur H. Waldie, Robert W. James, Timothy J. Canales, Michael L. White
  • Patent number: 5311454
    Abstract: A digital multiplier accumulator for performing the sum of products operation on two or more signal groups is described. The signal groups may be digitally coded and weighted. The multiplier accumulator will multiply selected signals from each signal group. Additionally, the multiplier accumulator can multiply the product of the signals by a scale factor. All of the products can then be summed to provide an analog output which represents the accumulated products of the digital inputs, scaled by the appropriate scale factor. The entire operation may be performed within a single logic element delay, since all the multiplication circuits operate in parallel and the summing is performed simultaneous to the multiplication. The digital multiplication is implemented with standard digital logic, while the analog multiplication and accumulation is implemented with a resistor array.
    Type: Grant
    Filed: February 8, 1993
    Date of Patent: May 10, 1994
    Assignee: Gulton Industries, Inc.
    Inventor: Timothy J. Canales