Patents by Inventor Timothy J. Charest

Timothy J. Charest has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SRAM and dual single ended bit sense for an SRAM
    Patent number: 7170799
    Abstract: A CMOS static random access memory (SRAM) and a bit select for the SRAM. The bit select includes a dual single-ended sense receiving a difference signal on a bit line pair and selectively sensing signals developing on each bit line independently of the other. Single ended outputs from the dual-ended sense are provided to an output driver. The output driver provides a pair of selectively-complementary output signals.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: January 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: Yuen H. Chan, Timothy J. Charest, Rajiv V. Joshi, Antonio Pelella
  • Cache late select circuit
    Patent number: 7054184
    Abstract: A late select circuit topology has pseudo-static circuits that provide fast dynamic circuit operation without the use of dynamic clock timing signals. An output from a selected set is enabled by the conjunction of bit line pulse and set select signal.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: May 30, 2006
    Assignee: International Business Machines Corporation
    Inventors: Yuen H. Chan, Timothy J. Charest, Antonio R. Pelella, John R. Rawlins
  • Clock driver and boundary latch for a multi-port SRAM
    Patent number: 6990038
    Abstract: A multi-port (e.g., two port) CMOS static random access memory (SRAM) with a local clock driver generating clocks for boundary latches. Local clocks select between address inputs clocked into the boundary latches. A read clock selects and latches a read address in the boundary latches. A second clock latches write addresses and, when appropriate, test data addresses.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: January 24, 2006
    Assignee: International Business Machines Corp.
    Inventors: Yuen H. Chan, Timothy J. Charest, Rajiv V. Joshi, Rolf Sautter
  • Programmable sense amplifier timing generator
    Patent number: 6958943
    Abstract: A SRAM sense amplifier timing circuit provides various delay settings for the sense amplifier enable signal (sae) and the sense amplifier reset signal (rse) in order to allow critical timing adjustments to be made for early mode, late mode conditions by varying the timing or with of the sense amplifier output pulse. These timing adjustments are programmable using scan in bits.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: October 25, 2005
    Assignee: International Business Machines Corporation
    Inventors: Yuen H. Chan, Timothy J. Charest, John R. Rawlins, Arthur D. Tuminaro, Jatinder K. Wadhwa, Otto M. Wagner