Abstract: An architecture for a computer system that has lower complexity than prior computer system architectures. In one embodiment the functionality that in prior computer system architectures resides in a central processing unit (CPU) is split between a CPU and a program control unit. This allows the CPU to have lower complexity and can permit the computer system to have greater flexibility and lower cost. In another embodiment the computer system contains a memory mapping unit. The memory mapping unit enables the computer system to use one of a plurality of peripherals without changing the instruction codes of the CPU thus increasing the flexibility of the computer system.

Abstract: An architecture for a computer system that has lower complexity than prior computer system architectures. In one embodiment the functionality that in prior computer system architectures resides in a central processing unit (CPU) is split between a CPU and a program control unit. This allows the CPU to have lower complexity and can permit the computer system to have greater flexibility and lower cost. In another embodiment the computer system contains a memory mapping unit. The memory mapping unit enables the computer system to use one of a plurality of peripherals without changing the instruction codes of the CPU thus increasing the flexibility of the computer system.

Abstract: A collision mitigation method used in a radio frequency identification (“RFID”) system is disclosed. A set of information classes (100) is assigned. A communication channel is assigned to each information class. Information is received on at least a first communication channel.

Abstract: A portable data device (400) having a power controller (430), a clock generator (428) and a digital circuit (432). The power controller (430) has an output signal. The output signal is representative of available power. The clock generator (428) is coupled to the output signal of the power controller (430) for generating a variable clock rate corresponding to the output signal. The digital [ath0228]circuit (432) is coupled to the clock generator (428), and the digital circuit (432) is controlled by the variable clock rate.

Abstract: A temperature compensated crystal oscillator (10), has a crystal oscillator circuit (12), a voltage controlled reactance element (30), a temperature compensation network (50), and a programmable DC-DC converter network (60) having an output (62) connected to the voltage controlled reactance element (30), or the temperature compensation network (50) or both. The DC-DC converter network (60) provides the capability of operating over an extended voltage range, by increasing the supply voltage to a level necessary to operate the voltage controlled reactance element (30). Much of this structure is adapted for use in an integrated circuit, and provides the advantages of minimizing power and current consumption.