Abstract: A method for integrating a slotted waveguide into a CMOS process is disclosed. A slot can be patterned on a SOI wafer by etching a first pad hard mask deposited over the wafer. The slot is then filled with a nitride plug material by depositing a second pad hard mask over the first pad hard mask. A waveguide in association with one or more electronic and photonic devices can also be patterned on the SOI wafer. The trenches can be filled with an isolation material and then polished. Thereafter, the first and second pad hard masks can be stripped from the wafer. The slot can once again be filled with the nitride plug material and patterned. After forming one or more electronic and photonic devices on the wafer using a standard CMOS process, a via can be opened down to the nitride plug and the nitride plug can then be removed.

Abstract: An improved method for manufacturing a lateral germanium detector is disclosed. A detector window is opened through an oxide layer to expose a doped single crystalline silicon layer situated on a substrate. Next, a single crystal germanium layer is grown within the detector window, and an amorphous germanium layer is grown on the oxide layer. The amorphous germanium layer is then polished to leave only a small portion around the single crystal germanium layer. A dielectric layer is deposited on the amorphous germanium layer and the single crystal germanium layer. Using resist masks and ion implants, multiple doped regions are formed on the single crystal germanium layer. After opening several oxide windows on the dielectric layer, a refractory metal layer is deposited on the doped regions to form multiple germanide layers.

Abstract: A method for integrating a slotted waveguide into a CMOS process is disclosed. A slot can be patterned on a SOI wafer by etching a first pad hard mask deposited over the wafer. The slot is then filled with a plug material by depositing a second pad hard mask over the first pad hard mask. A waveguide in association with one or more electronic and photonic devices can also be patterned on the SOI wafer. The trenches can be filled with an isolation material and then polished. Thereafter, the first and second pad hard masks can be stripped from the wafer. The slot can once again be filled with the plug material and patterned. After forming one or more electronic and photonic devices on the wafer using the standard CMOS process, a via can be opened up down to the nitride plug and the nitride plug can then be removed.

Abstract: An improved method for manufacturing a lateral germanium detector is disclosed. A detector window is opened through an oxide layer to expose a doped single crystalline silicon layer situated on a substrate. Next, a single crystal germanium layer is grown within the detector window, and an amorphous germanium layer is grown on the oxide layer. The amorphous germanium layer is then polished to leave only a small portion around the single crystal germanium layer. A dielectric layer is deposited on the amorphous germanium layer and the single crystal germanium layer. Using resist masks and ion implants, multiple doped regions are formed on the single crystal germanium layer. After opening several oxide windows on the dielectric layer, a refractory metal layer is deposited on the doped regions to form multiple germanide layers.

Abstract: A method for manufacturing multiple layers of waveguides is disclosed. Initially, a first cladding layer is deposited on a substrate, a first inner cladding layer is then deposited on the first cladding layer, and a first waveguide material is deposited on the first inner cladding layer. The first inner cladding layer and the first waveguide material are then selectively etched to form a first waveguide layer. Next, a second inner cladding layer followed by a second cladding layer are deposited on the first waveguide layer. The second inner cladding layer and the second cladding layer are removed by using a chemical-mechanical polishing process selective to the first waveguide material. A third inner cladding layer followed by a second waveguide material are deposited on the first waveguide material. The third inner cladding layer and the second waveguide material are then selectively etched to form a second waveguide layer.

Abstract: Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region.

Abstract: Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region.

Abstract: Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region.

Abstract: A method for fabricating photonic and electronic devices on a substrate is disclosed. Multiple slabs are initially patterned and etched on a layer of a substrate. An electronic device is fabricated on a first one of the slabs and a photonic device is fabricated on a second one of the slabs, such that the electronic device and the photonic device are formed on the same layer of the substrate.

Abstract: Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region.

Abstract: A method for fabricating a thermal optical heating element capable of adjusting refractive index of an optical waveguide is disclosed. A silicon block is initially formed on a cladding layer on a silicon substrate. The silicon block is located in close proximity to an optical waveguide. A cobalt layer is deposited on the silicon block. The silicon block is then annealed to cause the cobalt layer to react with the silicon block to form a cobalt silicide layer. The silicon block is again annealed to cause the cobalt silicide layer to transform into a cobalt di-silicide layer.

Abstract: A method for manufacturing multiple layers of waveguides is disclosed. Initially, a first cladding layer is deposited on a substrate, a first inner cladding layer is then deposited on the first cladding layer, and a first waveguide material is deposited on the first inner cladding layer. The first inner cladding layer and the first waveguide material are then selectively etched to form a first waveguide layer. Next, a second inner cladding layer followed by a second cladding layer are deposited on the first waveguide layer. The second inner cladding layer and the second cladding layer are removed by using a chemical-mechanical polishing process selective to the first waveguide material. A third inner cladding layer followed by a second waveguide material are deposited on the first waveguide material. The third inner cladding layer and the second waveguide material are then selectively etched to form a second waveguide layer.

Abstract: A method for fabricating photonic and electronic devices on a substrate is disclosed. Multiple slabs are initially patterned and etched on a layer of a substrate. An electronic device is fabricated on a first one of the slabs and a photonic device is fabricated on a second one of the slabs, such that the electronic device and the photonic device are formed on the same layer of the substrate.

Abstract: For those optical waveguides that require the deposition of a thick film and a high-temperature anneal to create an appropriate waveguide medium, wafer warping, bowing or dishing is reduced or eliminated by depositing a film of the same thickness on the backside of the wafer so as to relieve film stress during the deposition and annealing process. In one embodiment the waveguide medium is silicon oxynitride, although other depositable thick films may be utilized in place of the silicon oxynitride.

Abstract: A diagnostic tool based on a hybrid knowledge representation of a system under test is disclosed. Data collected from the system during its operation is compared to an event based representation of the system which comprises a plurality of predefined events. An event is recognized when the collected data matches the event's critical parameter. The recognized event is analyzed and an associated set of ambiguity group effects, which specify components to be re-ranked in an ambiguity group according to an associated ranking effect. Additonally, a symptom-fault model and a failure model can be analyzed to determine symptom-fault relationships and failure modes which are applicable to the system operation. Each applicable symptom-fault relationship and failure mode is also associated with a set of ambiguity group effects which rerank the ambiguity group. A structural model is analyzed starting with the components in the ambiguity group having the greatest probability of failure.

Abstract: Method and apparatus for performing system monitoring and diagnostics is disclosed. In performing system monitoring, data is acquired from the system under test and compared to an event model. The event model comprises a database having event records which pre-define events which can occur. Each event record includes a state vector dependency which lists the events which must occur prior to the pre-defined event occurring and one or more critical parameters defining the data which must occur during the system's performance for the event to have occurred. Event recognition is performed by comparing each event record to acquired operational data and to events already recognized. Associated with each event record in the database is an intelligent data acquisition action which defines an action to be taken as a result of the event record being recognized. These actions can modify the performance of the system being monitored or the acquisition of data.