Patents by Inventor Timothy J. Dalton
Timothy J. Dalton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10319870Abstract: An apparatus, system, and method are disclosed for a photovoltaic module, the photovoltaic module comprising a plurality of photovoltaic cells, a controllable infrared protection layer, and a protection switching means. The controllable infrared protection layer is for reducing the infrared radiation absorbed by the photovoltaic module, where the controllable infrared protection layer has a first state and a second state. When the infrared protection layer is in the first state the transmission of infrared radiation to the photovoltaic cells is higher than when the infrared protection layer is in the second state. The protection switching means is for switching the controllable infrared protection layer between the first state and the second state.Type: GrantFiled: September 21, 2010Date of Patent: June 11, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Timothy J. Dalton, Maxime Darnon, Rainer Krause, Gerd Pfeiffer, Kevin Prettyman, Carl J. Radens, Brian C. Sapp
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Patent number: 9472402Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.Type: GrantFiled: September 16, 2014Date of Patent: October 18, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Deok-kee Kim, Kenneth T. Settlemyer, Jr., Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens, Dirk Pfeiffer, Timothy J. Dalton, Katherina E. Babich, Arpan P. Mohorowala, Harald Okorn-Schmidt
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Patent number: 9201041Abstract: A sensing device includes a substrate having a source region and a drain region formed therein. A gate structure is formed over the substrate and includes a gate dielectric and a gate conductor. The gate conductor is formed on the gate dielectric and disposed between the source region and the drain region. A dielectric layer is formed over the substrate and has a depth configured to form a well over the gate conductor. A gate extension is formed in contact with or as part of the gate conductor and including a conductive material covering one or more surfaces of the well.Type: GrantFiled: August 14, 2013Date of Patent: December 1, 2015Assignee: GLOBALFOUNDRIES INCInventors: Timothy J. Dalton, Ashish V. Jagtiani, Ramachandran Muralidhar, Sufi Zafar
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Patent number: 9089080Abstract: Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.Type: GrantFiled: June 7, 2013Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Timothy J. Dalton, Elbert E. Huang, Sampath Purushothaman, Carl J. Radens
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Patent number: 9035465Abstract: Various embodiments include semiconductor structures. In one embodiment, the semiconductor structure includes a chip having a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.Type: GrantFiled: May 9, 2014Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Timothy J. Dalton, Mukta G. Farooq, John A. Fitzsimmons, Louis L. Hsu
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Publication number: 20150004802Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.Type: ApplicationFiled: September 16, 2014Publication date: January 1, 2015Inventors: Deok-kee Kim, Kenneth T. Settlemyer, JR., Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens, Dirk Pfeiffer, Timothy J. Dalton, Katherina E. Babich, Arpan P. Mohorowala, Harald Okorn-Schmidt
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Publication number: 20140370636Abstract: A sensing device includes a substrate having a source region and a drain region formed therein. A gate structure is formed over the substrate and includes a gate dielectric and a gate conductor. The gate conductor is formed on the gate dielectric and disposed between the source region and the drain region. A dielectric layer is formed over the substrate and has a depth configured to form a well over the gate conductor. A gate extension is formed in contact with or as part of the gate conductor and including a conductive material covering one or more surfaces of the well.Type: ApplicationFiled: August 14, 2013Publication date: December 18, 2014Applicant: International Business Machines CorporationInventors: Timothy J. Dalton, Ashish V. Jagtiani, Ramachandran Muralidhar, Sufi Zafar
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Publication number: 20140367748Abstract: A sensing device includes a substrate having a source region and a drain region formed therein. A gate structure is formed over the substrate and includes a gate dielectric and a gate conductor. The gate conductor is formed on the gate dielectric and disposed between the source region and the drain region. A dielectric layer is formed over the substrate and has a depth configured to form a well over the gate conductor. A gate extension is formed in contact with or as part of the gate conductor and including a conductive material covering one or more surfaces of the well.Type: ApplicationFiled: June 14, 2013Publication date: December 18, 2014Inventors: Timothy J. Dalton, Ashish V. Jagtiani, Ramachandran Muralidhar, Sufi Zafar
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Publication number: 20140332929Abstract: Various embodiments include semiconductor structures. In one embodiment, the semiconductor structure includes a chip having a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.Type: ApplicationFiled: May 9, 2014Publication date: November 13, 2014Applicant: International Business Machines CorporationInventors: Kangguo Cheng, Timothy J. Dalton, Mukta G. Farooq, John A. Fitzsimmons, Louis L. Hsu
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Patent number: 8828521Abstract: Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.Type: GrantFiled: June 7, 2013Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Timothy J. Dalton, Elbert E. Huang, Sampath Purushothaman, Carl J. Radens
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Patent number: 8802497Abstract: Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.Type: GrantFiled: March 28, 2012Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Louis Lu-Chen Hsu, Kangguo Cheng, Timothy J. Dalton, Mukta G. Farooq, John A. Fitzsimmons
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Patent number: 8791545Abstract: Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.Type: GrantFiled: July 27, 2012Date of Patent: July 29, 2014Assignee: International Business Machines CorporationInventors: Timothy J. Dalton, Ebenezer E. Eshun, Sarah L. Grunow, Zhong-Xiang He, Anthony K. Stamper
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Patent number: 8754400Abstract: A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.Type: GrantFiled: March 28, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Timothy J. Dalton, Bruce B. Doris, Ho-Cheol Kim, Carl J. Radens
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Publication number: 20130270224Abstract: Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.Type: ApplicationFiled: June 7, 2013Publication date: October 17, 2013Inventors: Lawrence A. Clevenger, Timothy J. Dalton, Elbert E. Huang, Sampath Purushothaman, Carl J. Radens
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Publication number: 20130273325Abstract: Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.Type: ApplicationFiled: June 7, 2013Publication date: October 17, 2013Inventors: Lawrence A. Clevenger, Timothy J. Dalton, Elbert E. Huang, Sampath Purushothaman, Carl J. Radens
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Patent number: 8513769Abstract: Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.Type: GrantFiled: April 22, 2010Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Charles T. Black, Matthew E. Colburn, Timothy J. Dalton, Daniel C. Edelstein, Wai-Kin Li, Anthony K. Stamper, Haining S. Yang
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Patent number: 8512849Abstract: Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.Type: GrantFiled: August 9, 2007Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Timothy J. Dalton, Elbert E. Huang, Sampath Purushothaman, Carl J. Radens
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Patent number: 8487401Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.Type: GrantFiled: January 27, 2012Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Timothy J. Dalton, Ebenezer E. Eshun, Jeffrey P. Gambino, Anthony K. Stamper, Kunal Vaed
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Patent number: 8486511Abstract: In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ? of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.Type: GrantFiled: March 26, 2012Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Charles T. Black, Timothy J. Dalton, Bruce B. Doris, Carl J. Radens
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Patent number: 8486512Abstract: In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ? of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.Type: GrantFiled: March 26, 2012Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Charles T. Black, Timothy J. Dalton, Bruce B. Doris, Carl J. Radens