Abstract: An integrated circuit development library is provided that characterizes several different logic device cells. The library specifies a number of different timing relationships for each of the logic device cells. These timing relationships are evaluated for each of the logic device cells at a first derating condition with a first simulator to provide a first set of derated condition values. The first set of derated condition values each correspond to one of the timing relationships evaluated. A first derating factor is calculated from the first set of derated condition values for estimating derated performance of an integrated circuit with a second simulator. This integrated circuit is developed from one or more of the logic device cells of the library.

Abstract: An integrated circuit development library is provided that characterizes several different logic device cells. The library specifies a number of different timing relationships for each of the logic device cells. These timing relationships are evaluated for each of the logic device cells at a first derating condition with a first simulator to provide a first set of derated condition values. The first set of derated condition values each correspond to one of the timing relationships evaluated. A first derating factor is calculated from the first set of derated condition values for estimating derated performance of an integrated circuit with a second simulator. This integrated circuit is developed from one or more of the logic device cells of the library.

Abstract: The optimization process of the present invention replaces the successive delay table generation approach of the prior art with one that minimizes delay table size by generating only those indices sufficient to satisfy the error limits prescribed. This is accomplished by generating only portions of the delay table by reducing the maximum load/ramp point for each generated portion until such time as the error percentage limit is not exceeded. The load/ramp indices for the generated delay tables are those defined for the interpolation comparison table. These non-linearly distributed indices force a greater indexing range within the higher load/ramp regions, where relative interpolation error percentage are not as great as those within the lower regions. Within the present invention, the maximum load/ramp point of the last optimized portion becomes the minimum of the next portion, while the maximum load/ramp of the interpolation table becomes the next max point.