Patents by Inventor Timothy J. Flaherty

Timothy J. Flaherty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11931157
    Abstract: Methods of generating a graphical representation of cardiac information on a display screen are provided. The method comprises: electronically creating or acquiring an anatomical model of the heart including multiple cardiac locations; electronically determining a data set of source information corresponding to cardiac activity at the multiple cardiac locations; electronically rendering the data set of source information in relation to the multiple cardiac locations on the display screen. Systems and devices for providing a graphical representation of cardiac information are also provided.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: March 19, 2024
    Assignee: ACUTUS MEDICAL, INC.
    Inventors: Christoph Scharf, Graydon E. Beatty, Gunter Scharf, Randell L. Werneth, Timothy J. Corvi, J. Christopher Flaherty, Maxwell R. Flaherty
  • Patent number: 4809212
    Abstract: A multiplier formed as a single integrated circuit chip generates in consecutive clock cycles the single-precision partial products of multiple-precision operands. Provision of an on-chip temporary register and "wrap-back" path avoids transmitting and externally storing intermediate results so that no clock cycles are used solely for data-transfers or other "overhead". Consecutive double-precision multiplications can be performed concurrently so that complete quadruple-precision products are generated every four cycles.
    Type: Grant
    Filed: June 19, 1985
    Date of Patent: February 28, 1989
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bernard J. New, Timothy J. Flaherty
  • Patent number: 4748582
    Abstract: A compact rectangular parallel multiplier array of Booth summation cells includes along a left edge a cell which reduces to two the number of sign-extension bits sufficient to generate subsequent intermediate products. The cell employs optimized logic circuitry which generates a sum, a carry and a guard bit for use during generation of the next most-significant intermediate product.
    Type: Grant
    Filed: June 19, 1985
    Date of Patent: May 31, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bernard J. New, Timothy J. Flaherty