Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

Abstract: A shim coil design technique determines a position and a geometry of a room temperature (RT) shim coil to provide both a desired field homogeneity and a desired B0 field setting time. The simultaneous satisfaction of both field homogeneity and field settling time is achieved without a reduction of flux leakage from the shim coil, modification of main magnet protection circuitry, and without necessarily decoupling of the shim coil from the overall main magnet.

Abstract: A superconducting coil circuit for a superconducting magnet includes a superconducting coil and a current limiting apparatus. The current limiting apparatus is connected in series with the superconducting coil and includes a mechanical device configured to cause a quench in the superconducting coil when a current in the superconducting coil reaches a predetermined value.