Abstract: An image sensor includes a plurality of photodetectors arranged in an array; and a plurality of transistors that are functionally shared by the photodetectors, wherein a distance of each photodetector to an adjacent transistor is substantially the same.

Abstract: An X-Y addressable active pixel sensor that uses serial shift registers to select image windows resulting in less semiconductor area being employed compared with prior art address decoding techniques comprising: an X-Y addressable imager having signal lines in both X and Y directions; at least one pair of serial shift registers operatively connected to the X-Y imager such that there is at least one serial shift register in each x and y directions to select signal lines to be applied to the X-Y imager; and loading circuitry that provides the capability for selectively addressing imaging sub-windows by placing bit patterns into the shift registers.

Abstract: An image sensor comprises a plurality of pixels arranged in rows and columns; at least two adjacent pixels in the same row each having a photodetector; a row select mechanism that allows independent selection of the adjacent pixels; and a common output signal node and output signal line for the two adjacent pixels.

Abstract: An image sensor comprises a plurality of pixels arranged in rows and columns; at least two adjacent pixels in the same row each having a photodetector; a row select mechanism that allows independent selection of the adjacent pixels; and a common output signal node and output signal line for the two adjacent pixels.

Abstract: An addressing circuit designed for implementation within the device being addressed that uses less silicon space by selecting the desired address with shift register outputs. A fast shift register is coupled to a slow shift register by a combinatorial circuit having inputs from the fast shift register and the slow shift register to providing the selected address. A timing circuit is electrically coupled to each the fast shift register and the slow shift register. A mode select circuit that is operatively coupled to at least one of either the fast shift register or the slow shift register. The mode select circuit comprises a Boolean logic circuit that is operatively coupled to at least one of either the slow shift register or the fast shift register, the Boolean logic circuit having at least one logical input that determine a first portion of at least one of the shift registers to be used and a second portion of at least one of the shift registers to be discarded.

Abstract: A single integrated circuit device is disclosed that is capable of selectively functioning in real time as either a sequential matrix multiplier, a parallel matrix multiplier, a convolver or a finite input response FIR filter in order to process image data. A core group of multipliers is used to provide the basic multiplication operation that is common to each of the desired image processing functions. Input data router unit, coefficient router units and an output data router unit are responsive to mode selection control signals, supplied to a mode selection port, to route the appropriate input data and coefficients to the core group of multipliers and to route the output of the adders to the correct output port(s) for each of the desired processing functions.

Abstract: A clock generator for producing a pulse that can be adjusted in width and position. The positive edge of an incoming clock signal is slowed by an adjustable rise time inverter with a selected bias voltage until a selected threshold voltage level is met by a Schmitt trigger. The output from the Schmitt trigger is directed through a similar delay circuit to establish the pulse width of the pulse.

Abstract: Oblong pads are fed horizontally on an input conveyor with their long axes pointed in the direction of movement. A support plate on a rotationally driven shaft carries several equiangularly spaced swinging levers having a long arm on one side of the swing axis and a short arm on the other. Followers on the short arms engage a stationary cam whose profile surrounds the shaft. As the levers revolve, the cam positions them so they meet incoming oblong pads squarely and sweep them around so their minor axes are pointed in the direction of movement as they drop onto an output conveyor which moves them in parallelism with the line of the input conveyor.