Abstract: A reverse battery protection circuits that provides an integrated reverse battery condition solution for protection of external NMOS switches during the reverse battery condition is disclosed herein. This reverse battery protection circuit minimizes power consumption during a reverse battery event wherein there is no need for mechanical adjustments such as heat sinking and clamping to extract the heat away from the silicon and not destroy the device. Specifically, the reverse battery protection circuit includes a push-pull gate drive circuit coupled between the first and second power supply rail. A protection subcircuit portion connects between a first output node and the second power supply rail to turn the external FET ‘on’ during the reverse battery condition. In particular, the protection subcircuit portion connects to the external FET device and includes a p-channel device connected between a second output node that biases the external FET device and a first diode.

Abstract: A control circuit (50) for a switch mode power converter having precise control of amplitude and frequency that does not exhibit overshoot error nor undershoot error during a fast charge cycle nor a fast discharge cycle, respectively. In a first embodiment, the control circuit (50) does not exhibit undershoot error during a fast discharge cycle. The control circuit (50) comprises an oscillator (70) for providing a periodic carrier signal comprising a sawtooth wave output signal (VST). The oscillator (70) includes a capacitor (CT2) charged and discharged to the power supply voltage (VCC) to provide the sawtooth wave output signal (VST). In addition, the oscillator (70) includes a switching circuit (65) coupled to the reference voltage level (Vref). The control circuit (50) further includes a gain circuit (64) having a reference voltage input (Vref2), voltage input (Vin) and an output (Out). The reference voltage input (Vref2) receives the reference voltage(Vref).

Abstract: A controlled area network (CAN) driver provides improved symmetry between its differential output signals CAN-H and CAN-L, and provides protection for its low voltage devices from voltage transients occurring on its output lines. A plurality of CAN drivers 80 are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.