Abstract: Systems, methods and articles of manufacture are disclosed for transposing array data on a SIMD multi-core processor architecture. A matrix in a SIMD format may be received. The matrix may comprise a SIMD conversion of a matrix M in a conventional data format. A mapping may be defined from each element of the matrix to an element of a SIMD conversion of a transpose of matrix M. A SIMD-transposed matrix T may be generated based on matrix M and the defined mapping. A row-wise algorithm may be applied to T, without modification, to operate on columns of matrix M.

Abstract: Techniques are disclosed for converting data into a format tailored for efficient multidimensional fast Fourier transforms (FFTS) on single instruction, multiple data (SIMD) multi-core processor architectures. The technique includes converting data from a multidimensional array stored in a conventional row-major order into SIMD format. Converted data in SIMD format consists of a sequence of blocks, where each block interleaves s rows such that SIMD vector processors may operate on s rows simultaneously. As a result, the converted data in SIMD format enables smaller-sized 1D FFTs to be optimized in SIMD multi-core processor architectures.

Abstract: Systems, methods and articles of manufacture are disclosed for compensating for motion of a subject during an MRI scan of the subject. k-space data may be received from the MRI scan of the subject. A first graphical image may be generated from a first set of data elements from the k-space data. Similarly, a second graphical image may be generated from a second set of data elements from the k-space data. An offset in pixels may be determined by which to translate the second graphical image from the first graphical image to compensate for the motion. The k-space data may be modified at a sub-pixel offset relative to the determined offset. A motion-compensated graphical image of the subject may be generated from the modified k-space data. Doing so reduces the search space evaluated to sharpen images generated from the k-space data.

Abstract: A technique is disclosed for distributed runtime diagnostics in hierarchical parallel environments. In one embodiment, a user is allowed to configure, during runtime, a processing element on which to perform diagnostics, an algorithm for the processing element to execute, a data set for the algorithm to execute against, a diagnostic function for the processing element to execute, a condition for executing the diagnostic function, and visualization parameters for memory local to the processing element. As a result, runtime diagnostics can be performed with sufficient degree of control and customization to aid debugging in a hierarchical parallel environment.

Abstract: Systems, methods and articles of manufacture are disclosed for transposing array data on a SIMD multi-core processor architecture. A matrix in a SIMD format may be received. The matrix may comprise a SIMD conversion of a matrix M in a conventional data format. A mapping may be defined from each element of the matrix to an element of a SIMD conversion of a transpose of matrix M. A SIMD-transposed matrix T may be generated based on matrix M and the defined mapping. A row-wise algorithm may be applied to T, without modification, to operate on columns of matrix M.

Abstract: Systems, methods and articles of manufacture are disclosed for compensating for motion of a subject during an MRI scan of the subject. k-space data may be received from the MRI scan of the subject. A first graphical image may be generated from a first set of data elements from the k-space data. Similarly, a second graphical image may be generated from a second set of data elements from the k-space data. An offset in pixels may be determined by which to translate the second graphical image from the first graphical image to compensate for the motion. The k-space data may be modified at a sub-pixel offset relative to the determined offset. A motion-compensated graphical image of the subject may be generated from the modified k-space data. Doing so reduces the search space evaluated to sharpen images generated from the k-space data.

Abstract: Techniques are disclosed for converting data into a format tailored for efficient multidimensional fast Fourier transforms (FFTS) on single instruction, multiple data (SIMD) multi-core processor architectures. The technique includes converting data from a multidimensional array stored in a conventional row-major order into SIMD format. Converted data in SIMD format consists of a sequence of blocks, where each block interleaves s rows such that SIMD vector processors may operate on s rows simultaneously. As a result, the converted data in SIMD format enables smaller-sized 1D FFTs to be optimized in SIMD multi-core processor architectures.

Abstract: A technique is disclosed for distributed runtime diagnostics in hierarchical parallel environments. In one embodiment, a user is allowed to configure, during runtime, a processing element on which to perform diagnostics, an algorithm for the processing element to execute, a data set for the algorithm to execute against, a diagnostic function for the processing element to execute, a condition for executing the diagnostic function, and visualization parameters for memory local to the processing element. As a result, runtime diagnostics can be performed with sufficient degree of control and customization to aid debugging in a hierarchical parallel environment.

Abstract: Embodiments of the invention provide a method, system and article of manufacture for parallel application load balancing and distributed work management. In one embodiment, a hierarchy of master nodes may be used to coordinate the actions of pools of worker nodes. Further, the activity of the master nodes may be controlled by a “coordinator” node. A coordinator node may be configured to distribute work unit descriptions to the collection of master nodes. If needed, embodiments of the invention may be scaled to deeper hierarchies.

Abstract: Embodiments of the invention provide a method, system and article of manufacture for parallel application load balancing and distributed work management. In one embodiment, a hierarchy of master nodes may be used to coordinate the actions of pools of worker nodes. Further, the activity of the master nodes may be controlled by a “coordinator” node. A coordinator node may be configured to distribute work unit descriptions to the collection of master nodes. If needed, embodiments of the invention may be scaled to deeper hierarchies.

Abstract: An integrated semiconductor VLSI chip design that increases the number of driver circuits, or groups of driver circuits, that can be simultaneously switched. Timed driver gating signals, or driver enable signals, are used, in conjunction with physical grouping of driver circuits on the chip, to isolate switching drivers from quiet drivers. This construction and arrangement minimizes detrimental effects usually caused by noise that is generated when driver circuits switch.