Abstract: A method and apparatus are disclosed for storing and accessing information of both asynchronous and synchronous devices using, for example, pointers having grey code counters which reduce code conversion logic and which are less susceptible to clock glitches, such as improper clock pulses due to internal circuit timing errors. Because the devices are less clock dependent, they do not require the imposition of critical paths during the placement and routing of a circuit layout. Further, fast and reliable accessing of information stored in memory devices can be achieved by multiplexing output bits addressed, for example, via the aforementioned grey code pointers.

Abstract: A two stage binary status register is set and reset by independent signals and comprises a first stage flip-flop, the output of which is connected to a second stage latch circuit. The set signals and the reset signals are applied to the two stages in a manner which insures that the output of the second stage latch always supplies an output corresponding to each set input signal, irrespective of the times of arrival of the set and reset signals, including all conditions of signal overlap and simultaneous arrival of both the set and reset signals.