Abstract: A circuit component comprises a row of transistors. The row may contain a first active FET with a source region and a drain region. The row may also contain a first active dummy FET that shares the source region and that also has a diffusion region. The row may also contain a second active FET and a second active dummy FET, positioned such that the active dummy FETs are located between the active FETs on the row. The row may also have an end positioned such that the first active dummy FET is between the end and the first active FET. A supply of current may be electrically connected to the source diffusion regions. A load region may be electrically connected to the drain region. The first active FET and the first active dummy FET may have gates that share a voltage source or that have their own voltage source.

Abstract: Certain aspects of the present disclosure are directed to a circuit for driving a signal at an output node. The circuit generally includes a voltage divider network having a first terminal coupled to the output node. The circuit also includes a first transistor having a gate coupled to a second terminal of the voltage divider network and a plurality of transistors. A gate of each of the plurality of transistors may be coupled to a respective tap node of the voltage divider network, and the plurality of transistors may include a third transistor having a source coupled to a drain of the first transistor. The circuit may also include a second transistor coupled to the first transistor and having a gate coupled to an input node of the circuit.

Abstract: Certain aspects of the present disclosure are directed to a circuit for driving a signal at an output node. The circuit generally includes a voltage divider network having a first terminal coupled to the output node. The circuit also includes a first transistor having a gate coupled to a second terminal of the voltage divider network and a plurality of transistors. A gate of each of the plurality of transistors may be coupled to a respective tap node of the voltage divider network, and the plurality of transistors may include a third transistor having a source coupled to a drain of the first transistor. The circuit may also include a second transistor coupled to the first transistor and having a gate coupled to an input node of the circuit.

Abstract: A circuit component comprises a row of transistors. The row may contain a first active FET with a source region and a drain region. The row may also contain a first active dummy FET that shares the source region and that also has a diffusion region. The row may also contain a second active FET and a second active dummy FET, positioned such that the active dummy FETs are located between the active FETs on the row. The row may also have an end positioned such that the first active dummy FET is between the end and the first active FET. A supply of current may be electrically connected to the source diffusion regions. A load region may be electrically connected to the drain region. The first active FET and the first active dummy FET may have gates that share a voltage source or that have their own voltage source.

Abstract: A method and circuit for implementing a broadband resonator for resonant clock distribution, and a design structure on which the subject circuit resides are provided. The circuit includes a pair of first inductors, and a second inductor and a capacitor coupled between a respective first end of the respective first inductors. An opposite free end of the respective first inductors is connected to a respective clock transmission line and connected in parallel to a load capacitance. A frequency response of the circuit includes two poles and a zero in a frequency band of the resonant clock distribution system.

Abstract: A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject circuit resides. Peak detectors are used to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock. Each detected levels is compared to a reference level to determine when to vary the turn off timing of a clock driver pull-up device and/or a clock driver pull-down device. A positive peak detector controls the turn off time of the pull-up device and a negative peak detector controls a turn off time of the pull-down device in the pulsed resonant driver.

Abstract: A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject circuit resides. Peak detectors are used to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock. Each detected levels is compared to a reference level to determine when to vary the turn off timing of a clock driver pull-up device and/or a clock driver pull-down device. A positive peak detector controls the turn off time of the pull-up device and a negative peak detector controls a turn off time of the pull-down device in the pulsed resonant driver.

Abstract: A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject circuit resides. Peak detectors are used to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock. Each detected levels is compared to a reference level to determine when to vary the turn off timing of a clock driver pull-up device and/or a clock driver pull-down device. A positive peak detector controls the turn off time of the pull-up device and a negative peak detector controls a turn off time of the pull-down device in the pulsed resonant driver.

Abstract: A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject circuit resides. Peak detectors are used to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock. Each detected levels is compared to a reference level to determine when to vary the turn off timing of a clock driver pull-up device and/or a clock driver pull-down device. A positive peak detector controls the turn off time of the pull-up device and a negative peak detector controls a turn off time of the pull-down device in the pulsed resonant driver.

Abstract: A method and circuit for implementing a broadband resonator for resonant clock distribution, and a design structure on which the subject circuit resides are provided. The circuit includes a pair of first inductors, and a second inductor and a capacitor coupled between a respective first end of the respective first inductors. An opposite free end of the respective first inductors is connected to a respective clock transmission line and connected in parallel to a load capacitance. A frequency response of the circuit includes two poles and a zero in a frequency band of the resonant clock distribution system.

Abstract: A gated differential logic circuit can include a header device having a first terminal coupled to a supply voltage, and a second terminal; a second header device having a third terminal coupled to the supply voltage, and a fourth terminal; a footer device having a fifth terminal coupled to ground, and a sixth terminal; and a second footer device having a seventh terminal coupled to ground, and an eighth terminal. The circuit further includes a driver circuit having a first supply terminal coupled to the second terminal and a first ground terminal coupled to the sixth terminal, and a second driver circuit having a second supply terminal coupled to the fourth terminal and a second ground terminal coupled to the eighth terminal. A capacitor can couple the first supply terminal to the second ground terminal, while a second capacitor may couple the second supply terminal to the first ground terminal.

Abstract: The present invention provides a power saving method and apparatus for powering a lower voltage device from a higher voltage power source. The apparatus includes a switch having an input coupled to an output of the higher voltage power source. The apparatus further includes a high-to-low voltage converter having an input coupled to an output of the switch. The apparatus also includes a power plug having an input coupled to an output of the high-to-low voltage power converter, and an output configured to receive a power socket of the low voltage device. Finally, the apparatus includes a switch actuator coupled to the power plug and the switch. When the power plug is operatively engaged within the power socket of the lower voltage device, the switch actuator closes the switch. When the power plug is operatively disengaged from the power plug, the switch actuator opens the switch.

Abstract: The present invention provides a power saving method and apparatus for powering a lower voltage device from a higher voltage power source. The apparatus includes a switch having an input coupled to an output of the higher voltage power source. The apparatus further includes a high-to-low voltage converter having an input coupled to an output of the switch. The apparatus also includes a power plug having an input coupled to an output of the high-to-low voltage power converter, and an output configured to receive a power socket of the low voltage device. Finally, the apparatus includes a switch actuator coupled to the power plug and the switch. When the power plug is operatively engaged within the power socket of the lower voltage device, the switch actuator closes the switch. When the power plug is operatively disengaged from the power plug, the switch actuator opens the switch.

Abstract: An integrated biquadratic, continuous-time filter section includes a plurality of operational transconductance amplifiers (OTAs). Simutaneously changing a transconductance (GM) of each of the OTAs is provided by adjusting a differential voltage applied to a plurality of differential transistor pairs of each OTA. Each of the OTAs include a plurality of current sources and a common mode feedback circuit for controlling a common mode output voltage level. Changing the transconductance of the OTA is independent of the common mode voltage level control.

Abstract: A method and apparatus are provided for translating small voltage continuous signals into large full supply signals to generate a clock signal. At least one oscillator input signal is applied to a first amplifier stage for generating an amplified voltage output signal. A first inverter is coupled to the first amplifier stage. A second inverter is coupled to the first inverter. An AC coupling capacitor couples the amplified voltage output signal to the first inverter input, and a feedback resistor is connected between the output and input of the first inverter.

Abstract: A method and apparatus are provided for adaptive chip trim adjustment for an integrated circuit. A plurality of switching devices have an unswitched state and a switched state. The unswitched state corresponds to one binary value, and the switched state corresponds to another binary value. A first trim word is provided by sensing the switching devices. The switching devices are temporarily bypassed, and an override bit pattern is supplied to simulate any desired pattern of the switching device states. The override bit pattern is used for simulating a switched or unswitched state for each of the plurality of switching devices.

Abstract: A circuit for a partial-response, maximum likelihood (PRML) magnetic recording channel stretches and shrinks pulses in particular write-data sequences. The circuit maintains precise tracking in the delays among multiple signals by sending them through the same number of identical circuits on the same chip. An external digital code varies the amount of delay in a clock signal so as to stretch and shrink the data pulses by different amounts.

Abstract: A differential analog input signal is level-shifted and converted to single-ended form. Its average value is compared to the midpoint of a set of reference voltages. A control signal proportional to the average value forces the average of the single-ended signal toward the midpoint voltage. The single-ended signal is converted to uncoded digital form by a parallel comparator bank, and is then converted to coded digital form.

Abstract: A circular translates an input signal about an input reference voltage to an output signal referenced to a different voltage. The input signal may be scaled, and multiple inputs may be scaled independently and summed. Shift networks transfer the input signal across a resistor on the input of a current mirror; the output signal appears across a resistor in an output of the mirror.