Patents by Inventor Timothy J. Siegel

Timothy J. Siegel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11182198
    Abstract: A method, system, and computer program product are provided for prioritizing transactions. A processor in a computing environment initiates the execution of a transaction. The processor includes a transactional core, and the execution of the transaction is performed by the transactional core. The processor obtains concurrent with the execution of the transaction by the transactional core, an indication of a conflict between the transaction and at least one other transaction being executed by an additional core in the computing environment. The processor determines if the transactional core includes an indicator and based on determining that the transactional core includes an indicator, the processor ignores the conflict and utilizing the transactional core to complete executing the transaction.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Siegel
  • Patent number: 11150905
    Abstract: A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Siegel
  • Patent number: 10430188
    Abstract: Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, whose execution comprises, based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: October 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christian Jacobi, Chung-Lung Kevin Shum, Timothy J Siegel, Gustav E Sittmann, III
  • Patent number: 9996472
    Abstract: A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F Greiner, Timothy J Siegel
  • Patent number: 9507646
    Abstract: A time-of-day (TOD) clock is leveraged to provide a high-resolution measure of the real time that is suitable for the indication of date and time to perform cycle-level thread synchronization. A time-of-day value provided by the time-of-day clock is used in a spin lock, along with a configurable mask, to meet a specified condition. The condition is met at regular time intervals and at the same time for all the hardware threads to be synchronized. When the condition is met and synchronization is reached, execution of the threads continues ensuring that the activity generated on each thread is in synchronization.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ramon Bertran, Pradip Bose, Alper Buyuktosunoglu, Timothy J. Siegel
  • Patent number: 9495306
    Abstract: According to some embodiments, a method for controlling a processor state with transient cache memory is described. The method may include identifying, via a processor, a memory section having a memory address, retrieving, via the processor, memory control information, and controlling the processor state by allowing a memory access to the transient cache memory based on the memory control information.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Dan F. Greiner, Michael Karl Gschwind, Christian Jacobi, Younes Manton, Anthony Saporito, Chung-Lung Kevin Shum, Joran S. C. Siu, Timothy J. Siegel
  • Patent number: 9454377
    Abstract: Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Billeci, James J. Bonanno, Adam B. Collura, Christian Jacobi, Anthony Saporito, Timothy J. Siegel
  • Patent number: 9280480
    Abstract: A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Dan F Greiner, Timothy J Siegel
  • Patent number: 9244856
    Abstract: An enhanced dynamic address translation facility is provided. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Dan F Greiner, Lisa C Heller, Damian L Osisek, Erwin Pfeffer, Timothy J Siegel, Charles F Webb
  • Patent number: 8631216
    Abstract: A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether the change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dan F Greiner, Lisa C Heller, Damian L Osisek, Erwin Pfeffer, Timothy J Siegel, Charles F Webb
  • Patent number: 7281115
    Abstract: An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: October 9, 2007
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Siegel, Lisa C. Heller, Erwin F. Pfeffer, Kenneth E. Plambeck
  • Patent number: 7020761
    Abstract: Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that address translation is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of page indices, which indicates whether the address translation can continue. If address translation can continue, the restriction is ignored. The processing unit includes a processor or a pageable entity, as examples.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: March 28, 2006
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Siegel, Bruce A. Wagar, Ute Gaertner, Lisa C. Heller, Erwin F. Pfeffer