Abstract: A method and apparatus for generating an address sequence in a memory device is provided. The method includes providing a memory array having a set of unique addresses, storing one of a first subset of the set of unique addresses in a first storage element, storing one of a second subset of the set of unique addresses in a second storage element, and generating a sequence of addresses to test the memory array. The sequence of addresses are formed by alternately outputting addresses stored in the first storage element and the second storage element such that the sequence of addresses causes each unique address of the set to transition only once. The sequence of addresses can be used to efficiently test the memory array during a built-in self-test (BIST).

Abstract: A technique for providing access to a first storage structure of a system includes exposing a first key of a plurality of first keys stored in a second storage structure in response to a select code based on a plurality of corresponding select records stored in one-time programmable storage elements of the second memory structure. The technique includes providing the first key as a current first key of a memory access controller. Only one of the plurality of first keys stored in the second storage structure may be exposed at a time and other first keys of the plurality of first keys stored in the second storage structure are inaccessible from the second storage structure at the time.

Abstract: A method and apparatus for generating an address sequence in a memory device is provided. The method includes providing a memory array having a set of unique addresses, storing one of a first subset of the set of unique addresses in a first storage element, storing one of a second subset of the set of unique addresses in a second storage element, and generating a sequence of addresses to test the memory array. The sequence of addresses are formed by alternately outputting addresses stored in the first storage element and the second storage element such that the sequence of addresses causes each unique address of the set to transition only once. The sequence of addresses can be used to efficiently test the memory array during a built-in self-test (BIST).

Abstract: A technique for providing access to a first storage structure of a system includes exposing a first key of a plurality of first keys stored in a second storage structure in response to a select code based on a plurality of corresponding select records stored in one-time programmable storage elements of the second memory structure. The technique includes providing the first key as a current first key of a memory access controller. Only one of the plurality of first keys stored in the second storage structure may be exposed at a time and other first keys of the plurality of first keys stored in the second storage structure are inaccessible from the second storage structure at the time.

Abstract: An error correcting device is provided that has an input connectable to receive one or more data units, an error detection module arranged to identify a presence of one or more errors in a received data unit of the one or more data units and to provide an error detection signal for the received data unit, an error correction module arranged to perform an error correction processing on the received data unit and provide a corrected data unit, and a correction evaluation module arranged to perform a comparison of the received data unit with the corrected data unit and to generate a correction error signal depending on a result of the comparison and the error detection signal.

Abstract: A mechanism for express storage of sensor data in response to an indication of a power fluctuation, power brownout or blackout that can affect operation of a microcontroller is provided. Embodiments provide a flash memory having memory space allocated to express storage of the sensor data, and a protocol machine configured to provide the desired information to reserved registers associated with express program/erase operations accessing the allocated memory space.

Abstract: A microcontroller that includes a secure firmware flash controller is provided. The secure firmware flash controller utilizes a hardware assisted boot sequence that performs a firmware code validation. If the firmware code fails validation for any reason, the firmware flash controller locks out access to the firmware RAM and firmware flash controller, and passes control back to the microcontroller for further measures that are protected by security protocols on the microcontroller.

Abstract: An error correcting device is provided that has an input connectable to receive one or more data units, an error detection module arranged to identify a presence of one or more errors in a received data unit of the one or more data units and to provide an error detection signal for the received data unit, an error correction module arranged to perform an error correction processing on the received data unit and provide a corrected data unit, and a correction evaluation module arranged to perform a comparison of the received data unit with the corrected data unit and to generate a correction error signal depending on a result of the comparison and the error detection signal.

Abstract: A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.

Abstract: A method for tracking alteration of a non-volatile storage includes receiving a request to modify a tracked region of the non-volatile storage. In response to the request, it is determined whether or not a modification of data stored in a non-erasable one-time programmable (NEOTP) alteration log region has occurred. In response to determining that the modification of the data stored in the NEOTP alteration log region has occurred, the tracked region of non-volatile storage is modified in response to the request. In response to determining that the modification of the data stored in the NEOTP alteration log region has not occurred, the request to modify the tracked region of the non-volatile memory is denied.

Abstract: A portion of a programmable memory device is configured as a one-time programmable (OTP) memory, where in response to a write access to the memory device, a memory controller determines whether the write access is associated with a memory location designated as an OTP memory location. If so, the memory controller performs a read of the memory location, and allows the write access only if each memory cell of the memory location is in an un-programmed state. Thus, only a single write access to an OTP memory location is permitted, and subsequent write attempts are disallowed. Further, to enhance detection of programmed cells, the read of the OTP memory location is performed with a lower read voltage than a read voltage associated with a write access to a non-OTP memory location, thereby improving detection of programmed memory cells in the OTP memory location.

Abstract: A method for accessing a memory includes receiving a first address wherein the first address corresponds to a demand fetch, receiving a second address wherein the second address corresponds to a speculative prefetch, providing first data from the memory in response to the demand fetch in which the first data is accessed asynchronous to a system clock, and providing second data from the memory in response to the speculative prefetch in which the second data is accessed synchronous to the system clock. The memory may include a plurality of pipeline stages in which providing the first data in response to the demand fetch is performed such that each pipeline stage is self-timed independent of the system clock and providing the second data in response to the speculative prefetch is performed such that each pipeline stage is timed based on the system clock to be synchronous with the system clock.

Abstract: A method for accessing a memory includes receiving a first address wherein the first address corresponds to a demand fetch, receiving a second address wherein the second address corresponds to a speculative prefetch, providing first data from the memory in response to the demand fetch in which the first data is accessed asynchronous to a system clock, and providing second data from the memory in response to the speculative prefetch in which the second data is accessed synchronous to the system clock. The memory may include a plurality of pipeline stages in which providing the first data in response to the demand fetch is performed such that each pipeline stage is self-timed independent of the system clock and providing the second data in response to the speculative prefetch is performed such that each pipeline stage is timed based on the system clock to be synchronous with the system clock.

Abstract: A method for tracking alteration of a non-volatile storage includes receiving a request to modify a tracked region of the non-volatile storage. In response to the request, it is determined whether or not a modification of data stored in a non-erasable one-time programmable (NEOTP) alteration log region has occurred. In response to determining that the modification of the data stored in the NEOTP alteration log region has occurred, the tracked region of non-volatile storage is modified in response to the request. In response to determining that the modification of the data stored in the NEOTP alteration log region has not occurred, the request to modify the tracked region of the non-volatile memory is denied.

Abstract: A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.

Abstract: A portion of a programmable memory device is configured as a one-time programmable (OTP) memory, where in response to a write access to the memory device, a memory controller determines whether the write access is associated with a memory location designated as an OTP memory location. If so, the memory controller performs a read of the memory location, and allows the write access only if each memory cell of the memory location is in an un-programmed state. Thus, only a single write access to an OTP memory location is permitted, and subsequent write attempts are disallowed. Further, to enhance detection of programmed cells, the read of the OTP memory location is performed with a lower read voltage than a read voltage associated with a write access to a non-OTP memory location, thereby improving detection of programmed memory cells in the OTP memory location.

Abstract: Methods and apparatus for programming a non-volatile memory array comprising addressable units are provided. The addressable units are configured to store at least a main portion and an error correction portion. An exemplary method for programming the non-volatile memory array includes, in response to a first condition, switching from an error correction enabled mode to an error correction disabled mode and programming at least the main portion of at least one addressable unit of the non-volatile memory array in the error correction disabled mode. The exemplary method further includes, in response to a second condition, switching from the error correction disabled mode to an error correction fill mode and programming at least the error correction portion of the at least one addressable unit of the non-volatile memory array in the error correction fill mode.

Abstract: Methods and apparatus for programming a non-volatile memory array comprising addressable units are provided. The addressable units are configured to store at least a main portion and an error correction portion. An exemplary method for programming the non-volatile memory array includes, in response to a first condition, switching from an error correction enabled mode to an error correction disabled mode and programming at least the main portion of at least one addressable unit of the non-volatile memory array in the error correction disabled mode. The exemplary method further includes, in response to a second condition, switching from the error correction disabled mode to an error correction fill mode and programming at least the error correction portion of the at least one addressable unit of the non-volatile memory array in the error correction fill mode.