Patents by Inventor Timothy J. Van Hook

Timothy J. Van Hook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6256655
    Abstract: A method and system for performing floating point operations in unnormalized format using a floating point accumulator. The present invention provides a set of floating point instructions and a floating point accumulator which stores the results of the operations in unnormalized format. Since the present invention operates on and stores floating point numbers in unnormalized format, the normalization step in the implementation of the floating point operations, which is typically required in the prior art, is readily eliminated. The present invention thus provides significant improvements in both time and space efficiency over prior art implementations of floating point operations. In digital signal processing applications, where floating point operations are used extensively for sums of products calculations, the performance improvements afforded by the present invention are further magnified by the elimination of normalization in each of numerous iterations of multiply and add instructions.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: July 3, 2001
    Assignee: Silicon Graphics, Inc.
    Inventors: Gulbin Ezer, Sudhaker Rao, Timothy J. van Hook
  • Patent number: 6239810
    Abstract: A low cost high performance three dimensional (3D) graphics system can model a world in three dimensions and project the model onto a two dimensional viewing plane selected based on a changeable viewpoint. The viewpoint can be changed on an interactive, real time basis by operating user input controls such as game controllers. The system rapidly produces a corresponding changing image (which can include animated cartoon characters or other animation) on the screen of a color television set. The richly featured high performance low cost system gives consumers the chance to interact in real time right inside magnificent virtual 3D worlds to provide a high degree of image realism, excitement and flexibility. An optimum feature set/architecture (including a custom designed graphics/audio coprocessor) provides high quality fast moving 3D images and digital stereo sound for video game play and other graphics applications.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: May 29, 2001
    Assignees: Nintendo Co., Ltd., Silicon Graphics, Inc.
    Inventors: Timothy J. Van Hook, Howard H. Cheng, Anthony P. DeLaurier, Carroll P. Gossett, Robert J. Moore, Stephen J. Shepard, Harold S. Anderson, John Princen, Jeffrey C. Doughty, Nathan F. Pooley, Byron Sheppard, Genyo Takeda, Shuhei Kato
  • Patent number: 6166748
    Abstract: A low cost high performance three dimensional (3D) graphics system is disclosed that can model a world in three dimensions and project the model onto a two dimensional viewing plane selected based on a changeable viewpoint. The viewpoint can be changed on an interactive, real time basis by operating user input controls such as game controllers. The system rapidly produces a corresponding changing image (which can include animated cartoon characters or other animation) on the screen of a color television set.The richly featured high performance low cost system is intended to give consumers the chance to interact in real time right inside magnificent virtual 3D worlds to provide a high degree of image realism, excitement and flexibility. An optimum feature set/architecture (including a custom designed graphics/audio coprocessor) provides high quality fast moving 3D images and digital stereo sound for video game play and other graphics applications.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: December 26, 2000
    Assignees: Nintendo Co., Ltd., Silicon Graphics Inc.
    Inventors: Timothy J. Van Hook, Howard H. Cheng, Anthony P. DeLaurier, Carroll P. Gossett, Robert J. Moore, Stephen J. Shepard, Harold S. Anderson, John Princen, Jeffrey C. Doughty, Nathan F. Pooley, Byron Sheppard, Genyo Takeda, Shuhei Kato
  • Patent number: 6075906
    Abstract: A system and method for scaling image streams that use motion vectors is disclosed. The system combines an error term with a predicted term in order to produce a display value. The system operates on image components represented in the spatial and frequency domains. The system processes motion vectors in the spatial domain. The motion vectors are scaled. The integral part of the scaled motion vector addresses a framestore. The fractional portion of the scaled motion vector is input to a nonlinear filter which determines the value of image components for a location that does not correspond with an image location in the framestore. The output of the nonlinear filter comprises the predicted terms. Data in the frequency domain is processed more efficiently by reducing the size of a block of data by appropriate filtering. The resulting data is transformed to the spatial domain.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: June 13, 2000
    Assignee: Silicon Graphics Inc.
    Inventors: Stephen C. Fenwick, Timothy J. Van Hook, Gregory Humpreys Efland
  • Patent number: 5982939
    Abstract: A system and method of antialiasing edges of a texture that is being projected onto a polygon surface are described. The system operates by determining an initial opacity value of a pixel of the polygon surface as mapped into the texture, and then adjusting the initial opacity value so as to achieve a single pixel wide projected texture edge. This adjustment is performed by determining whether the initial opacity value is less than a threshold, where the threshold represents a desired alpha value of pixels along a projected texture edge. If the initial opacity value is less than the threshold, then a new opacity value of the pixel is set equal to a value denoting full transparency. If, instead, the initial opacity value is greater than the threshold, then a new opacity value of the pixel is set equal to a value denoting full opacity.
    Type: Grant
    Filed: November 17, 1997
    Date of Patent: November 9, 1999
    Assignee: Silicon Graphics, Inc.
    Inventor: Timothy J. Van Hook
  • Patent number: 5938756
    Abstract: The integer execution unit (IEU) of a central processing unit (CPU) is provided with a graphics status register (GSR) for storing a graphics data scaling factor and a graphics data alignment address offset. Additionally, the CPU is provided with a graphics execution unit (GRU) for executing a number of graphics operations in accordance to the graphics data scaling factor and alignment address offset, the graphics data having a number of graphics data formats. In one embodiment, the GRU is also used to execute a number of graphics data addition, subtraction, rounding, expansion, merge, alignment, multiplication, logical, compare, and pixel distance operations. The graphics data operations are categorized into a first and a second category, and the GRU concurrently executes one graphics operations from each category.
    Type: Grant
    Filed: April 19, 1996
    Date of Patent: August 17, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Timothy J. Van Hook, Leslie Dean Kohn, Robert Yung
  • Patent number: 5933157
    Abstract: The integer execution unit (IEU) of a central processing unit (CPU) is provided with a graphics status register (GSR) for storing a graphics data scaling factor and a graphics data alignment address offset. Additionally, the CPU is provided with a graphics execution unit (GRU) for executing a number of graphics operations in accordance to the graphics data scaling factor and alignment address offset, the graphics data having a number of graphics data formats. In one embodiment, the GRU is also used to execute a number of graphics data addition, subtraction, rounding, expansion, merge, alignment, multiplication, logical, compare, and pixel distance operations. The graphics data operations are categorized into a first and a second category, and the GRU concurrently executes one graphics operations from each category.
    Type: Grant
    Filed: April 19, 1996
    Date of Patent: August 3, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Timothy J. Van Hook, Leslie Dean Kohn, Robert Yung
  • Patent number: 5931945
    Abstract: A partial store instruction and associated logic for storing selected bytes of a group of bytes in a register to a designated memory location. A mask in a separate register is used to enable particular bytes to be written, with only enabled bytes being written to the final location. The mask can be previously generated as a result of a comparison or other operation. The creation of the mask and the execution of a partial store instruction can also be used as a prefetch instruction, eliminating the need for a separate opcode for a prefetch.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: August 3, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Robert Yung, Leslie D. Kohn, Timothy J. Van Hook
  • Patent number: 5933650
    Abstract: The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: August 3, 1999
    Assignee: MIPS Technologies, Inc.
    Inventors: Timothy J. van Hook, Peter Hsu, William A. Huffman, Henry P. Moreton, Earl A. Killian
  • Patent number: 5812147
    Abstract: Instruction methods for moving data between memory and a vector register file while performing data formatting. The methods are processed by a processor having a vector register file and a memory unit. The methods are useful in the graphics art because they allow more efficient movement and processing of raster formatted graphics data. The vector register file has a number of vector registers (e.g., 32) that each contain multi-bits of storage (e.g., 128 bits). In one class of instructions, eight byte locations within memory are simultaneously loaded into eight separate 16 bit locations within a register of the register file. The data can be integer or fraction and signed or unsigned. The data can also be stored from the register file back to memory. In a second class of instructions, alternate locations of a memory qaudword are selected and simultaneously loaded in the register file.
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: September 22, 1998
    Assignee: Silicon Graphics, Inc.
    Inventors: Timothy J. Van Hook, Henry P. Moreton, Michael L. Fuccio, Robert W. Pryor, Jr., Charles F. Tuffli, III
  • Patent number: 5742277
    Abstract: A system and method for antialiasing silhouette edges are described herein. A video interface accesses the frame buffer to retrieve a foreground color of an edge pixel that falls on the silhouette edge. The video interface estimates a background color of the edge pixel based on foreground colors of neighboring pixels that are proximate to the edge pixel. Then, the video interface interpolates between the foreground color and the estimated background color to determine an output color of the edge pixel. Also described herein are a system and method of internal edge antialiasing.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: April 21, 1998
    Assignee: Silicon Graphics, Inc.
    Inventors: Carroll Phillip Gossett, Timothy J. Van Hook
  • Patent number: 5734874
    Abstract: A central processing unit (CPU) is provided with a graphics execution unit (GRU), including a graphics status register (GSR), for executing a number of graphics operations in accordance to a graphics data scaling factor and an alignment address offset stored in the GSR, the graphics data having a number of graphics data formats. In one embodiment, the GRU is also used to execute a number of graphics data addition, subtraction, rounding, expansion, merge, alignment, multiplication, logical, compare, and pixel distance operations. The graphics data operations are categorized into a first and a second category, and the GRU concurrently executes one graphics operations from each category.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: March 31, 1998
    Assignee: Sun Microsystems, Inc.
    Inventors: Timothy J. Van Hook, Leslie Dean Kohn, Robert Yung
  • Patent number: 5638500
    Abstract: An apparatus and method calculate outcodes directly from an integral representation of a floating point number defining a certain coordinate of a point of an object to be displayed. Such calculations under software control are absent any Boolean conventional branch instructions which impede system performance and utilize an integer unit rather than a floating point unit so as to enable transformations of viewing parameters and calculations of outcodes to be performed in a concurrent manner.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: June 10, 1997
    Assignee: Sun Microsystems, Inc.
    Inventors: Walter E. Donovan, Timothy J. Van Hook