Abstract: Integrated circuits with memory built-in self-test (BIST) logic and methods of testing using the same are disclosed. The method includes setting an address window for locating defects in a memory array. The method further includes comparing output data of the memory array to expected data to determine that a defect exists at location “M” in the memory array within the address window. The method further includes storing, in registers, the address M and a resultant bit fail vector associated with the location “M” of the defect found in the memory array. The method further includes resetting the registers to a null value and resetting the address window with a new minimum and maximum address pair, to compare the output data of the memory array to the expected data within the reset address window which excludes address M.

Abstract: Integrated circuits with memory built-in self-test (BIST) logic and methods of testing using the same are disclosed. The method includes setting an address window for locating defects in a memory array. The method further includes comparing output data of the memory array to expected data to determine that a defect exists at location “M” in the memory array within the address window. The method further includes storing, in registers, the address M and a resultant bit fail vector associated with the location “M” of the defect found in the memory array. The method further includes resetting the registers to a null value and resetting the address window with a new minimum and maximum address pair, to compare the output data of the memory array to the expected data within the reset address window which excludes address M.

Abstract: A method and circuit for adjusting the read margin of a self-timed memory array. The electronic circuit, including: a memory cell array including a sense amplifier self-timed decode circuit adapted to set a base read time delay of the memory cell array; and a read delay adjustment circuit coupled to the memory cell array, the read delay adjustment circuit adapted to adjust the base read time delay of the memory array based on an operating frequency of the memory cell array.

Abstract: Test data is provided through shift registers, operated at a high clock rate comparable to or exceeding a normal high speed clock rate of a chip being tested, to each of a plurality of scan chains configured from registers present on the chip; respective latches of which are connected to inputs and outputs of logic array partitions to be tested. Reduced test clock rate of input and output circuits of the scan chains is accommodated by high speed source and sink shift registers. The source and sink registers are fully loaded and unloaded between consecutive test clock signals and test signals are preferably applied to and collected from the chip in a single serial string through a single pair of tester input/output pins.

Abstract: A microprocessor having two on-board clock generators. The faster clock generator controls the microprocessor during normal, synchronous mode. The slower clock generator controls the microprocessor when the bus must be accessed, or during "snoop" mode which is invoked when another entry signals intent to use the bus.A microprocessor having two on-board clock generators. The faster clock generator controls the microprocessor during normal, synchronous mode. The slower clock generator controls the microprocessor when the bus must be accessed, or during "snoop" mode which is invoked when another entity signals intent to use the bus.