Abstract: Systems and methods include receiving (102) a plurality of symbols that are part of a defined Digital Signal Processing (DSP) frame for coherent optical communication, wherein the DSP frame structure has a messaging channel incorporated therein that includes a subset of the plurality of symbols; capturing (104) multiple samples of the messaging channel; and determining (106) a message in the messaging channel based on analysis of the multiple samples. The method can further include transmitting (108), in the messaging channel, a reply to the message with the reply being repeated multiple times. The analysis is performed prior to Forward Error Correction (FEC) decoding on the data path.

Abstract: An optical system includes a transmitter including transmitter circuitry configured to cause transmission of a transmitted optical signal over a fiber link on an X polarization and a Y polarization; and a receiver including receiver circuitry configured to receive a received optical signal from the fiber link on the X polarization and the Y polarization, wherein the transmitter circuitry is configured to cause State of Polarization (SOP) changes on the X polarization and the Y polarization for a test of the fiber link. The transmitter circuitry and the receiver circuitry are built-in with the transmitter and the receiver, respectively, for performance of the test.

Abstract: Systems and methods include receiving a plurality of symbols that are part of a defined Digital Signal Processing (DSP) frame for coherent optical communication, wherein the DSP frame structure has a messaging channel incorporated therein that includes a subset of the plurality of symbols; capturing multiple samples of the messaging channel; and determining a message in the messaging channel based on analysis of the multiple samples. The method can further include transmitting, in the messaging channel, a reply to the message with the reply being repeated multiple times. The analysis is performed prior to Forward Error Correction (FEC) decoding on the data path.

Abstract: Systems and methods include receiving a plurality of symbols that are part of a defined Digital Signal Processing (DSP) frame for coherent optical communication, wherein the DSP frame structure has a messaging channel incorporated therein that includes a subset of the plurality of symbols; capturing multiple samples of the messaging channel; and determining a message in the messaging channel based on analysis of the multiple samples. The method can further include transmitting, in the messaging channel, a reply to the message with the reply being repeated multiple times. The analysis is performed prior to Forward Error Correction (FEC) decoding on the data path.

Abstract: Upon receiving a communications signal conveying symbols at a symbol period T, a receiver applies filter coefficients to a digital representation of the communications signal, thereby generating filtered signals having a shape in the frequency domain characterized by a bandwidth expansion factor ?, where components of the filtered signals correspond to angular frequencies ? = - ? ? ( 1 + ? ) T ? ? … - ? ? ( 1 - ? ) T , + ? ? ( 1 - ? ) T ? ? … + ? ? ( 1 + ? ) T . The receiver calculates first-order components from a first phase derivative of the components at a first differential distance, second-order components from a second phase derivative of the first-order components at a second differential distance, and composite second-order components from an average of the second-order components over multiple time intervals.

Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

Abstract: Upon receiving a communications signal conveying symbols at a symbol period T, a receiver applies filter coefficients to a digital representation of the communications signal, thereby generating filtered signals characterized by a substantially raised cosine shape in the frequency domain with a roll-off factor ?, where components of the filtered signals correspond to angular frequencies ? = - ? ? ( 1 + ? ) T ? … - ? ? ( 1 - ? ) T , + ? ? ( 1 - ? ) T ? … + ? ? ( 1 + ? ) T . The receiver calculates first-order components from a first phase derivative of the components at a first differential distance, second-order components from a second phase derivative of the first-order components at a second differential distance, and composite second-order components from an average of the second-order components over multiple time intervals.

Abstract: Managing clock-data recovery for a modulated signal from a communication channel comprises: receiving the modulated signal and providing one or more analog signals, providing one or more digital input streams from samples of the analog signals, and processing the digital input streams to provide decoded digital data. The processing comprises: determining the decoded digital data based on information modulated over a plurality of frequency elements associated with the modulated signal, based at least in part on transforms of the digital input streams; a clock signal based on clock recovery from the digital input streams; and determining a clock phase error estimate associated with the determined clock signal based at least in part on a sum that includes different weights multiplied by different respective summands corresponding to different sets of frequency elements.

Abstract: An optical system includes a transmitter including transmitter circuitry configured to cause transmission of a transmitted optical signal over a fiber link on an X polarization and a Y polarization; and a receiver including receiver circuitry configured to receive a received optical signal from the fiber link on the X polarization and the Y polarization, wherein the transmitter circuitry is configured to cause State of Polarization (SOP) changes on the X polarization and the Y polarization for a test of the fiber link. The transmitter circuitry and the receiver circuitry are built-in with the transmitter and the receiver, respectively, for performance of the test.

Abstract: A system includes an optical transmitter including a transmitter Phase Lock Loop (PLL) circuit; an optical receiver connected to the optical transmitter and including a receiver PLL circuit; and circuitry configured to inject a test stimulus to a clock causing jitter in one of the transmitter PLL circuitry and the receiver PLL circuit, wherein the test stimulus is set for characterizing the jitter tolerance of optical receiver. As well, a circuit that injects SOP transient at the transmitter is included. It is configured to test the tolerance of optical receiver to handle fast change in the SOP state. The optical receiver is configured to determine if the system is operational at a jitter value due to the test stimulus based on compliance to one or more thresholds including any of a target Bit Error Rate, a Forward-Error-Correction (FEC) hit, and a jitter Root Mean Square (RMS).

Abstract: A system includes an optical transmitter including a transmitter Phase Lock Loop (PLL) circuit; an optical receiver connected to the optical transmitter and including a receiver PLL circuit; and circuitry configured to inject a test stimulus to a clock causing jitter in one of the transmitter PLL circuitry and the receiver PLL circuit, wherein the test stimulus is set for characterizing the jitter tolerance of optical receiver. As well, a circuit that injects SOP transient at the transmitter is included. It is configured to test the tolerance of optical receiver to handle fast change in the SOP state. The optical receiver is configured to determine if the system is operational at a jitter value due to the test stimulus based on compliance to one or more thresholds including any of a target Bit Error Rate, a Forward-Error-Correction (FEC) hit, and a jitter Root Mean Square (RMS).

Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

Abstract: A method and device for performing Hforward error (FEC) correction avoidance based upon predicted block code reliability in a communications device is provided. An avoidance unit comprising a metric computation unit and a decision unit generates a reliability metric based upon a received code block. The reliability metric is compared to a reliability threshold, and the forward error correction decoder in the communications device is disabled if the metric is below or equal to the threshold.

Abstract: A method and device for performing forward error (FEC) correction avoidance based upon predicted block code reliability in a communications device is provided. An avoidance unit comprising a metric computation unit and a decision unit generates a reliability metric based upon a received code block. The reliability metric is compared to a reliability threshold, and the forward error correction decoder in the communications device is disabled if the metric is below or equal to the threshold.

Abstract: A method and device for performing forward error (FEC) correction avoidance based upon predicted block code reliability in a communications device is provided. An avoidance unit comprising a metric computation unit and a decision unit generates a reliability metric based upon a received code block. The reliability metric is compared to a reliability threshold, and the forward error correction decoder in the communications device is disabled if the metric is below or equal to the threshold.

Abstract: Aspects of the present application include using adaptive measurement intervals to improve RSSI scan accuracy. A method may involve determining a first power value in respect of a first measurement time interval, determining whether or not the first power value meets at least one criterion, when the first power value does not meet the at least one criterion, determining at least one additional power value, selecting at least one power value from a set of power values that have been determined, the set including the first power value and the at least one additional power value, and determining the power value for use in cell selection or cell re-selection based on the selected at least one power value. The methods may be applied to any cell selection or re-selection scheme for which an adaptive measurement interval may be beneficial.

Abstract: Described herein are methods and devices for use in telecommunication cell selection and re-selection for which there may be multiple different sizes of transmission bandwidth configurations in a telecommunications operating band. For each of a plurality of channel hypotheses, in which each channel hypothesis has a hypothetical occupied portion and a hypothetical guard band portion, a respective metric is calculated based on a power value for the hypothetical occupied portion and a power value for the hypothetical guard band portion. Based on the metrics determined for the plurality of channel hypotheses, at least one channel hypothesis is selected for further processing for cell selection or re-selection. The metric is calculated by determining a difference between the power value for the hypothetical occupied portion and the power value for the hypothetical guard band portion.